-/* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_span.c,v 1.1 2002/10/30 12:51:52 alanh Exp $ */
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
* Keith Whitwell <keith@tungstengraphics.com>
*/
-#include "glheader.h"
-#include "imports.h"
+#include "main/glheader.h"
+#include "main/imports.h"
+#include "main/colormac.h"
#include "swrast/swrast.h"
-#include "colormac.h"
#include "r200_context.h"
+#include "radeon_buffer.h"
#include "r200_ioctl.h"
#include "r200_state.h"
#include "r200_span.h"
#define DBG 0
-#define LOCAL_VARS \
- r200ContextPtr rmesa = R200_CONTEXT(ctx); \
- r200ScreenPtr r200Screen = rmesa->r200Screen; \
- __DRIscreenPrivate *sPriv = rmesa->dri.screen; \
- __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
- GLuint pitch = r200Screen->frontPitch * r200Screen->cpp; \
- GLuint height = dPriv->h; \
- char *buf = (char *)(sPriv->pFB + \
- rmesa->state.color.drawOffset + \
- (dPriv->x * r200Screen->cpp) + \
- (dPriv->y * pitch)); \
- char *read_buf = (char *)(sPriv->pFB + \
- rmesa->state.pixel.readOffset + \
- (dPriv->x * r200Screen->cpp) + \
- (dPriv->y * pitch)); \
- GLuint p; \
- (void) read_buf; (void) buf; (void) p
-
-#define LOCAL_DEPTH_VARS \
- r200ContextPtr rmesa = R200_CONTEXT(ctx); \
- r200ScreenPtr r200Screen = rmesa->r200Screen; \
- __DRIscreenPrivate *sPriv = rmesa->dri.screen; \
- __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
- GLuint height = dPriv->h; \
- GLuint xo = dPriv->x; \
- GLuint yo = dPriv->y; \
- char *buf = (char *)(sPriv->pFB + r200Screen->depthOffset); \
- (void) buf
-
-#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
-
-
-#define CLIPPIXEL( _x, _y ) \
- ((_x >= minx) && (_x < maxx) && (_y >= miny) && (_y < maxy))
-
-
-#define CLIPSPAN( _x, _y, _n, _x1, _n1, _i ) \
- if ( _y < miny || _y >= maxy ) { \
- _n1 = 0, _x1 = x; \
- } else { \
- _n1 = _n; \
- _x1 = _x; \
- if ( _x1 < minx ) _i += (minx-_x1), n1 -= (minx-_x1), _x1 = minx; \
- if ( _x1 + _n1 >= maxx ) n1 -= (_x1 + n1 - maxx); \
- }
-
-#define Y_FLIP( _y ) (height - _y - 1)
+/*
+ * Note that all information needed to access pixels in a renderbuffer
+ * should be obtained through the gl_renderbuffer parameter, not per-context
+ * information.
+ */
+#define LOCAL_VARS \
+ struct radeon_renderbuffer *rrb = (void *) rb; \
+ const __DRIdrawablePrivate *dPriv = rrb->dPriv; \
+ const GLuint bottom = dPriv->h - 1; \
+ GLuint p; \
+ (void) p;
+#define LOCAL_DEPTH_VARS \
+ struct radeon_renderbuffer *rrb = (void *) rb; \
+ const __DRIdrawablePrivate *dPriv = rrb->dPriv; \
+ const GLuint bottom = dPriv->h - 1; \
+ GLuint xo = dPriv->x; \
+ GLuint yo = dPriv->y;
-#define HW_LOCK()
+#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
-#define HW_CLIPLOOP() \
- do { \
- __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
- int _nc = dPriv->numClipRects; \
- \
- while ( _nc-- ) { \
- int minx = dPriv->pClipRects[_nc].x1 - dPriv->x; \
- int miny = dPriv->pClipRects[_nc].y1 - dPriv->y; \
- int maxx = dPriv->pClipRects[_nc].x2 - dPriv->x; \
- int maxy = dPriv->pClipRects[_nc].y2 - dPriv->y;
-
-#define HW_ENDCLIPLOOP() \
- } \
- } while (0)
+#define Y_FLIP(Y) (bottom - (Y))
+
+#define HW_LOCK()
#define HW_UNLOCK()
/* 16 bit, RGB565 color spanline and pixel functions
*/
-
-#define GET_SRC_PTR(_x, _y) (read_buf + _x * 2 + _y * pitch)
-#define GET_DST_PTR(_x, _y) ( buf + _x * 2 + _y * pitch)
#define SPANTMP_PIXEL_FMT GL_RGB
#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
-#define TAG(x) r200##x##_RGB565
-#define TAG2(x,y) r200##x##_RGB565##y
+#define TAG(x) radeon##x##_RGB565
+#define TAG2(x,y) radeon##x##_RGB565##y
+#define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y))
#include "spantmp2.h"
/* 32 bit, ARGB8888 color spanline and pixel functions
*/
-
-#define GET_SRC_PTR(_x, _y) (read_buf + _x * 4 + _y * pitch)
-#define GET_DST_PTR(_x, _y) ( buf + _x * 4 + _y * pitch)
#define SPANTMP_PIXEL_FMT GL_BGRA
#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
-#define TAG(x) r200##x##_ARGB8888
-#define TAG2(x,y) r200##x##_ARGB8888##y
+#define TAG(x) radeon##x##_ARGB8888
+#define TAG2(x,y) radeon##x##_ARGB8888##y
+#define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y))
#include "spantmp2.h"
* manner as the engine. In each case, the linear block address (ba)
* is calculated, and then wired with x and y to produce the final
* memory address.
+ * The chip will do address translation on its own if the surface registers
+ * are set up correctly. It is not quite enough to get it working with hyperz too...
*/
-#define BIT(x,b) ((x & (1<<b))>>b)
-static GLuint r200_mba_z32( r200ContextPtr rmesa,
- GLint x, GLint y )
-{
- GLuint pitch = rmesa->r200Screen->frontPitch;
- GLuint b = ((y & 0x3FF) >> 4) * ((pitch & 0xFFF) >> 5) + ((x & 0x3FF) >> 5);
- GLuint a =
- (BIT(x,0) << 2) |
- (BIT(y,0) << 3) |
- (BIT(x,1) << 4) |
- (BIT(y,1) << 5) |
- (BIT(x,3) << 6) |
- (BIT(x,4) << 7) |
- (BIT(x,2) << 8) |
- (BIT(y,2) << 9) |
- (BIT(y,3) << 10) |
- (((pitch & 0x20) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y,4)))) << 11) |
- ((b >> 1) << 12);
- return a;
-}
-
-static GLuint r200_mba_z16( r200ContextPtr rmesa, GLint x, GLint y )
-{
- GLuint pitch = rmesa->r200Screen->frontPitch;
- GLuint b = ((y & 0x3FF) >> 4) * ((pitch & 0xFFF) >> 6) + ((x & 0x3FF) >> 6);
- GLuint a =
- (BIT(x,0) << 1) |
- (BIT(y,0) << 2) |
- (BIT(x,1) << 3) |
- (BIT(y,1) << 4) |
- (BIT(x,2) << 5) |
- (BIT(x,4) << 6) |
- (BIT(x,5) << 7) |
- (BIT(x,3) << 8) |
- (BIT(y,2) << 9) |
- (BIT(y,3) << 10) |
- (((pitch & 0x40) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y,4)))) << 11) |
- ((b >> 1) << 12);
- return a;
-}
-
-
/* 16-bit depth buffer functions
*/
+#define VALUE_TYPE GLushort
+
#define WRITE_DEPTH( _x, _y, d ) \
- *(GLushort *)(buf + r200_mba_z16( rmesa, _x + xo, _y + yo )) = d;
+ *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) = d
#define READ_DEPTH( d, _x, _y ) \
- d = *(GLushort *)(buf + r200_mba_z16( rmesa, _x + xo, _y + yo ));
+ d = *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo)
-#define TAG(x) r200##x##_16
+#define TAG(x) radeon##x##_z16
#include "depthtmp.h"
+
/* 24 bit depth, 8 bit stencil depthbuffer functions
*/
+#define VALUE_TYPE GLuint
+
#define WRITE_DEPTH( _x, _y, d ) \
do { \
- GLuint offset = r200_mba_z32( rmesa, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
+ GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \
+ GLuint tmp = *_ptr; \
tmp &= 0xff000000; \
tmp |= ((d) & 0x00ffffff); \
- *(GLuint *)(buf + offset) = tmp; \
+ *_ptr = tmp; \
} while (0)
#define READ_DEPTH( d, _x, _y ) \
- d = *(GLuint *)(buf + r200_mba_z32( rmesa, _x + xo, \
- _y + yo )) & 0x00ffffff;
+ do { \
+ d = (*(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo)) & 0x00ffffff); \
+ }while(0)
-#define TAG(x) r200##x##_24_8
+#define TAG(x) radeon##x##_z24_s8
#include "depthtmp.h"
*/
#define WRITE_STENCIL( _x, _y, d ) \
do { \
- GLuint offset = r200_mba_z32( rmesa, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
+ GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \
+ GLuint tmp = *_ptr; \
tmp &= 0x00ffffff; \
tmp |= (((d) & 0xff) << 24); \
- *(GLuint *)(buf + offset) = tmp; \
+ *_ptr = tmp; \
} while (0)
#define READ_STENCIL( d, _x, _y ) \
do { \
- GLuint offset = r200_mba_z32( rmesa, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
+ GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \
+ GLuint tmp = *_ptr; \
tmp &= 0xff000000; \
d = tmp >> 24; \
} while (0)
-#define TAG(x) r200##x##_24_8
+#define TAG(x) radeon##x##_z24_s8
#include "stenciltmp.h"
-/*
- * This function is called to specify which buffer to read and write
- * for software rasterization (swrast) fallbacks. This doesn't necessarily
- * correspond to glDrawBuffer() or glReadBuffer() calls.
- */
-static void r200SetBuffer( GLcontext *ctx,
- GLframebuffer *colorBuffer,
- GLuint bufferBit )
+void r200InitSpanFuncs( GLcontext *ctx )
{
- r200ContextPtr rmesa = R200_CONTEXT(ctx);
-
- switch ( bufferBit ) {
- case DD_FRONT_LEFT_BIT:
- if ( rmesa->doPageFlip && rmesa->sarea->pfCurrentPage == 1 ) {
- rmesa->state.pixel.readOffset = rmesa->r200Screen->backOffset;
- rmesa->state.pixel.readPitch = rmesa->r200Screen->backPitch;
- rmesa->state.color.drawOffset = rmesa->r200Screen->backOffset;
- rmesa->state.color.drawPitch = rmesa->r200Screen->backPitch;
- } else {
- rmesa->state.pixel.readOffset = rmesa->r200Screen->frontOffset;
- rmesa->state.pixel.readPitch = rmesa->r200Screen->frontPitch;
- rmesa->state.color.drawOffset = rmesa->r200Screen->frontOffset;
- rmesa->state.color.drawPitch = rmesa->r200Screen->frontPitch;
- }
- break;
- case DD_BACK_LEFT_BIT:
- if ( rmesa->doPageFlip && rmesa->sarea->pfCurrentPage == 1 ) {
- rmesa->state.pixel.readOffset = rmesa->r200Screen->frontOffset;
- rmesa->state.pixel.readPitch = rmesa->r200Screen->frontPitch;
- rmesa->state.color.drawOffset = rmesa->r200Screen->frontOffset;
- rmesa->state.color.drawPitch = rmesa->r200Screen->frontPitch;
- } else {
- rmesa->state.pixel.readOffset = rmesa->r200Screen->backOffset;
- rmesa->state.pixel.readPitch = rmesa->r200Screen->backPitch;
- rmesa->state.color.drawOffset = rmesa->r200Screen->backOffset;
- rmesa->state.color.drawPitch = rmesa->r200Screen->backPitch;
- }
- break;
- default:
- _mesa_problem(ctx, "Bad bufferBit in %s", __FUNCTION__);
- break;
- }
+ struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
+ swdd->SpanRenderStart = radeonSpanRenderStart;
+ swdd->SpanRenderFinish = radeonSpanRenderFinish;
}
-/* Move locking out to get reasonable span performance (10x better
- * than doing this in HW_LOCK above). WaitForIdle() is the main
- * culprit.
- */
-
-static void r200SpanRenderStart( GLcontext *ctx )
-{
- r200ContextPtr rmesa = R200_CONTEXT( ctx );
-
- R200_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
- r200WaitForIdleLocked( rmesa );
-
- /* Read & rewrite the first pixel in the frame buffer. This should
- * be a noop, right? In fact without this conform fails as reading
- * from the framebuffer sometimes produces old results -- the
- * on-card read cache gets mixed up and doesn't notice that the
- * framebuffer has been updated.
- *
- * In the worst case this is buggy too as p might get the wrong
- * value first time, so really need a hidden pixel somewhere for this.
- */
- {
- int p;
- volatile int *read_buf = (volatile int *)(rmesa->dri.screen->pFB +
- rmesa->state.pixel.readOffset);
- p = *read_buf;
- *read_buf = p;
- }
-}
-static void r200SpanRenderFinish( GLcontext *ctx )
-{
- r200ContextPtr rmesa = R200_CONTEXT( ctx );
- _swrast_flush( ctx );
- UNLOCK_HARDWARE( rmesa );
-}
-void r200InitSpanFuncs( GLcontext *ctx )
+/**
+ * Plug in the Get/Put routines for the given driRenderbuffer.
+ */
+void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb)
{
- r200ContextPtr rmesa = R200_CONTEXT(ctx);
- struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
-
- swdd->SetBuffer = r200SetBuffer;
-
- switch ( rmesa->r200Screen->cpp ) {
- case 2:
- r200InitPointers_RGB565( swdd );
- break;
-
- case 4:
- r200InitPointers_ARGB8888( swdd );
- break;
-
- default:
- break;
- }
-
- switch ( rmesa->glCtx->Visual.depthBits ) {
- case 16:
- swdd->ReadDepthSpan = r200ReadDepthSpan_16;
- swdd->WriteDepthSpan = r200WriteDepthSpan_16;
- swdd->ReadDepthPixels = r200ReadDepthPixels_16;
- swdd->WriteDepthPixels = r200WriteDepthPixels_16;
- break;
-
- case 24:
- swdd->ReadDepthSpan = r200ReadDepthSpan_24_8;
- swdd->WriteDepthSpan = r200WriteDepthSpan_24_8;
- swdd->ReadDepthPixels = r200ReadDepthPixels_24_8;
- swdd->WriteDepthPixels = r200WriteDepthPixels_24_8;
-
- swdd->ReadStencilSpan = r200ReadStencilSpan_24_8;
- swdd->WriteStencilSpan = r200WriteStencilSpan_24_8;
- swdd->ReadStencilPixels = r200ReadStencilPixels_24_8;
- swdd->WriteStencilPixels = r200WriteStencilPixels_24_8;
- break;
-
- default:
- break;
- }
-
- swdd->SpanRenderStart = r200SpanRenderStart;
- swdd->SpanRenderFinish = r200SpanRenderFinish;
+ if (rrb->base.InternalFormat == GL_RGB5) {
+ radeonInitPointers_RGB565(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_RGBA8) {
+ radeonInitPointers_ARGB8888(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) {
+ radeonInitDepthPointers_z16(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) {
+ radeonInitDepthPointers_z24_s8(&rrb->base);
+ } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
+ radeonInitStencilPointers_z24_s8(&rrb->base);
+ }
}