#include "tnl/t_pipeline.h"
#include "swrast_setup/swrast_setup.h"
+#include "radeon_buffer.h"
+#include "radeon_mipmap_tree.h"
+#include "radeon_cs.h"
+#include "common_context.h"
+#include "common_cmdbuf.h"
#include "r200_context.h"
#include "r200_ioctl.h"
#include "r200_state.h"
VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
-#if 0
-static int ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
{
r200ContextPtr r200 = R200_CONTEXT(ctx);
BATCH_LOCALS(&r200->radeon);
struct radeon_renderbuffer *rrb;
uint32_t cbpitch;
+ uint32_t zbpitch;
+ uint32_t dwords = atom->cmd_size;
GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate;
-
+
+ /* output the first 7 bytes of context */
+ BEGIN_BATCH_NO_AUTOSTATE(dwords);
+ OUT_BATCH_TABLE(atom->cmd, 5);
+
+ rrb = r200->radeon.state.depth.rrb;
+ if (!rrb) {
+ OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHOFFSET]);
+ OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHPITCH]);
+ } else {
+ zbpitch = (rrb->pitch / rrb->cpp);
+ OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+ OUT_BATCH(zbpitch);
+ }
+
+ OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
+ OUT_BATCH(atom->cmd[CTX_CMD_1]);
+ OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
+ OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
+
rrb = r200->radeon.state.color.rrb;
if (r200->radeon.radeonScreen->driScreen->dri2.enabled) {
rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
}
if (!rrb || !rrb->bo) {
- fprintf(stderr, "no rrb\n");
- return;
+ OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
+ } else {
+ OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
}
- cbpitch = (rrb->pitch / rrb->cpp);
- if (rrb->cpp == 4)
- ;
- else
- ;
+ OUT_BATCH(atom->cmd[CTX_CMD_2]);
+
+ if (!rrb || !rrb->bo) {
+ OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
+ } else {
+ cbpitch = (rrb->pitch / rrb->cpp);
+ if (rrb->cpp == 4)
+ ;
+ else
+ ;
+ if (r200->radeon.sarea->tiling_enabled)
+ cbpitch |= R200_COLOR_TILE_ENABLE;
+ OUT_BATCH(cbpitch);
+ }
+
+ if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
+ OUT_BATCH_TABLE((atom->cmd + 14), 4);
+
+ END_BATCH();
}
-#endif
-static int tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
{
+ r200ContextPtr r200 = R200_CONTEXT(ctx);
+ BATCH_LOCALS(&r200->radeon);
+ uint32_t dwords = atom->cmd_size;
+ int i = atom->idx;
+ radeonTexObj *t = r200->state.texture.unit[i].texobj;
+
+ BEGIN_BATCH_NO_AUTOSTATE(dwords);
+ fprintf(stderr,"atom state is %x, %x %x %x %x %x\n", atom->cmd[0],
+ atom->cmd[1],
+ atom->cmd[2],
+ atom->cmd[3],
+ atom->cmd[4],
+ atom->cmd[5]);
+ OUT_BATCH_TABLE(atom->cmd, 10);
+ if (t && !t->image_override) {
+ fprintf(stderr,"emitting reloc for %d\n", i);
+ OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
+ RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ } else if (!t) {
+
+ OUT_BATCH(atom->cmd[10]);
+ }
+ END_BATCH();
}
+static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+ r200ContextPtr r200 = R200_CONTEXT(ctx);
+ BATCH_LOCALS(&r200->radeon);
+ uint32_t dwords = atom->cmd_size;
+ int i = atom->idx;
+ radeonTexObj *t = r200->state.texture.unit[i].texobj;
+ GLuint size;
+
+ BEGIN_BATCH_NO_AUTOSTATE(dwords);
+ OUT_BATCH_TABLE(atom->cmd, 3);
+
+ fprintf(stderr,"total size is %d\n", t->mt->totalsize);
+ if (t && !t->image_override) {
+ size = t->mt->totalsize / 6;
+ OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ }
+ END_BATCH();
+}
/* Initialize the context's hardware state.
*/
else
ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
- // rmesa->hw.ctx.emit = ctx_emit;
+ rmesa->hw.ctx.emit = ctx_emit;
ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
}
+
+ for (i = 0; i < 5; i++)
+ rmesa->hw.tex[i].emit = tex_emit;
if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
+ for (i = 0; i < 5; i++)
+ rmesa->hw.cube[i].emit = cube_emit;
}
else {
ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
}
+
if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
projects / mesa.git / blobdiff