i965: Move device info initialization to common code

[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c

diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index d9d1a0ed227f0782477cd05c77238dad5a49e6ca..41c3df710e51359a51fb2722184760ff011f1f17 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -31,11 +31,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *   Keith Whitwell <keithw@vmware.com>
  */
 
+#include "main/errors.h"
 #include "main/glheader.h"
 #include "main/imports.h"
 #include "main/enums.h"
-#include "main/colormac.h"
 #include "main/api_arrayelt.h"
+#include "main/state.h"
 
 #include "swrast/swrast.h"
 #include "vbo/vbo.h"
@@ -49,7 +50,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r200_state.h"
 #include "radeon_queryobj.h"
 
-#include "xmlpool.h"
+#include "util/xmlpool.h"
 
 /* New (1.3) state mechanism.  3 commands (packet, scalar, vector) in
  * 1.3 cmdbuffers allow all previous state to be updated as well as
@@ -230,7 +231,7 @@ static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \
 static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \
 {                                                                      \
    r200ContextPtr rmesa = R200_CONTEXT(ctx);                           \
-   return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
+   return (!rmesa->radeon.TclFallback && !_mesa_arb_vertex_program_enabled(ctx) && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
 }
 
 #define TCL_OR_VP_CHECK( NM, FLAG, ADD )                       \
@@ -245,18 +246,18 @@ static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom )
 {                                                                      \
    r200ContextPtr rmesa = R200_CONTEXT(ctx);                           \
    (void) atom;                                                                \
-   return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
+   return (!rmesa->radeon.TclFallback && _mesa_arb_vertex_program_enabled(ctx) && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
 }
 
 CHECK( always, GL_TRUE, 0 )
 CHECK( always_add4, GL_TRUE, 4 )
 CHECK( never, GL_FALSE, 0 )
 CHECK( tex_any, ctx->Texture._MaxEnabledTexImageUnit != -1, 0 )
-CHECK( tf, (ctx->Texture._MaxEnabledTexImageUnit != -1 && !ctx->ATIFragmentShader._Enabled), 0 );
-CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled, 0 )
-   CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled), 0 )
-CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 )
-CHECK( afs, ctx->ATIFragmentShader._Enabled, 0 )
+CHECK( tf, (ctx->Texture._MaxEnabledTexImageUnit != -1 && !_mesa_ati_fragment_shader_enabled(ctx)), 0 );
+CHECK( pix_zero, !_mesa_ati_fragment_shader_enabled(ctx), 0 )
+CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !_mesa_ati_fragment_shader_enabled(ctx)), 0 )
+CHECK( afs_pass1, (_mesa_ati_fragment_shader_enabled(ctx) && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 )
+CHECK( afs, _mesa_ati_fragment_shader_enabled(ctx), 0 )
 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE )
 CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 + 4*5 - CUBE_STATE_SIZE )
 TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 )
@@ -272,8 +273,8 @@ TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE, 0 )
 TCL_OR_VP_CHECK( tcl_or_vp_add2, GL_TRUE, 2 )
 VP_CHECK( tcl_vp, GL_TRUE, 0 )
 VP_CHECK( tcl_vp_add4, GL_TRUE, 4 )
-VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 4 )
-VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 4 )
+VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->arb.NumNativeInstructions > 64, 4 )
+VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->arb.NumNativeParameters > 96, 4 )
 
 #define OUT_VEC(hdr, data) do {                        \
     drm_radeon_cmd_header_t h;                                 \
@@ -453,12 +454,15 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
        atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
    else switch (rrb->base.Base.Format) {
    case MESA_FORMAT_B5G6R5_UNORM:
+   case MESA_FORMAT_R5G6B5_UNORM:
        atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
        break;
    case MESA_FORMAT_B4G4R4A4_UNORM:
+   case MESA_FORMAT_A4R4G4B4_UNORM:
        atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
        break;
    case MESA_FORMAT_B5G5R5A1_UNORM:
+   case MESA_FORMAT_A1R5G5B5_UNORM:
        atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
        break;
    default: