projects / mesa.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
radeon: glReadBuffer set _NEW_BUFFERS, not _NEW_PIXEL
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index f7149c36e20da99c2247db4b622e3de6425e69d0..be57ac3163877f32fe0adf6b72813a5ee2baa5b7 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -166,22 +166,6 @@ static struct {
 /* =============================================================
  * State initialization
  */
-
-void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
-{
-   struct radeon_state_atom *l;
-
-   fprintf(stderr, msg);
-   fprintf(stderr, ": ");
-
-   foreach(l, &rmesa->radeon.hw.atomlist) {
-      if (l->dirty || rmesa->radeon.hw.all_dirty)
-        fprintf(stderr, "%s, ", l->name);
-   }
-
-   fprintf(stderr, "\n");
-}
-
 static int cmdpkt( r200ContextPtr rmesa, int id ) 
 {
    drm_radeon_cmd_header_t h;
@@ -305,11 +289,12 @@ VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 9
     OUT_BATCH_TABLE((data), h.vectors.count);                          \
   } while(0)
 
-#define OUT_VECLINEAR(hdr, data) do {                  \
-    drm_radeon_cmd_header_t h;                                 \
-    uint32_t _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8);        \
-    uint32_t _sz = h.veclinear.count * 4;                              \
+#define OUT_VECLINEAR(hdr, data) do {                                  \
+    drm_radeon_cmd_header_t h;                                         \
+    uint32_t _start, _sz;                                              \
     h.i = hdr;                                                         \
+    _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8);         \
+    _sz = h.veclinear.count * 4;                                       \
     OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0));               \
     OUT_BATCH(0);                                                      \
     OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0));             \
@@ -515,11 +500,13 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
      atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
    }
 
-   dwords = 14;
+   dwords = 10;
    if (drb)
      dwords += 6;
    if (rrb)
      dwords += 6;
+   if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
+     dwords += 4;
 
    /* output the first 7 bytes of context */
    BEGIN_BATCH_NO_AUTOSTATE(dwords);
@@ -565,21 +552,17 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    uint32_t dwords = atom->cmd_size;
    int i = atom->idx;
    radeonTexObj *t = r200->state.texture.unit[i].texobj;
+   radeon_mipmap_level *lvl;
 
    if (t && t->mt && !t->image_override)
      dwords += 2;
    BEGIN_BATCH_NO_AUTOSTATE(dwords);
+   /* is this ok even with drm older than 1.18? */
    OUT_BATCH_TABLE(atom->cmd, 10);
 
    if (t && t->mt && !t->image_override) {
-     if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
-       lvl = &t->mt->levels[0];
-       OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
-                       RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-     } else {
-        OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
-                    RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-     }
+     OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
+                 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
    } else if (!t) {
      /* workaround for old CS mechanism */
      OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
@@ -606,27 +589,21 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
        if (!t->mt && !t->bo)
                hastexture = 0;
    }
-   dwords += 1;
+
    if (hastexture)
      dwords += 2;
    else
      dwords -= 2;
    BEGIN_BATCH_NO_AUTOSTATE(dwords);
 
-   OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (24 * i), 8));
-   OUT_BATCH_TABLE((atom->cmd + 1), 9);
+   OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (24 * i), 7));
+   OUT_BATCH_TABLE((atom->cmd + 1), 8);
 
    if (hastexture) {
      OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
      if (t->mt && !t->image_override) {
-        if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
-            lvl = &t->mt->levels[0];
-           OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
-                       RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-        } else {
-           OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
-                    RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-        }
+        OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
+                 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
       } else {
        if (t->bo)
             OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
@@ -641,21 +618,21 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
 {
    r200ContextPtr r200 = R200_CONTEXT(ctx);
    BATCH_LOCALS(&r200->radeon);
-   uint32_t dwords = atom->cmd_size;
-   int i = atom->idx;
+   uint32_t dwords = 2;
+   int i = atom->idx, j;
    radeonTexObj *t = r200->state.texture.unit[i].texobj;
-   GLuint size;
+   radeon_mipmap_level *lvl;
 
-   BEGIN_BATCH_NO_AUTOSTATE(dwords + (2 * 5));
-   OUT_BATCH_TABLE(atom->cmd, 3);
+   BEGIN_BATCH_NO_AUTOSTATE(dwords + (4 * 5));
+   OUT_BATCH_TABLE(atom->cmd, 2);
 
    if (t && !t->image_override) {
-     size = t->mt->totalsize / 6;
-     OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0);
-     OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0);
-     OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0);
-     OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0);
-     OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0);
+     lvl = &t->mt->levels[0];
+     for (j = 1; j <= 5; j++) {
+       OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
+       OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
+                       RADEON_GEM_DOMAIN_VRAM, 0, 0);
+     }
    }
    END_BATCH();
 }
@@ -672,21 +649,15 @@ void r200InitState( r200ContextPtr rmesa )
    switch ( ctx->Visual.depthBits ) {
    case 16:
       rmesa->radeon.state.depth.clear = 0x0000ffff;
-      rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
       rmesa->radeon.state.stencil.clear = 0x00000000;
       break;
    case 24:
    default:
       rmesa->radeon.state.depth.clear = 0x00ffffff;
-      rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
       rmesa->radeon.state.stencil.clear = 0xffff0000;
       break;
    }
 
-   /* Only have hw stencil when depth buffer is 24 bits deep */
-   rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
-                                    ctx->Visual.depthBits == 24 );
-
    rmesa->radeon.Fallback = 0;
 
    rmesa->radeon.hw.max_state_size = 0;