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r300/compiler: Implement KILP opcode.
[mesa.git] / src / mesa / drivers / dri / r300 / compiler / radeon_opcodes.c
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
index ffe2de1a87376789a96313955e568dfc8f5685cc..04f234f11d8cc4936a9a4f08bf0ca8a6d411dc9c 100644 (file)
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
@@ -26,6 +26,9 @@
  */
 
 #include "radeon_opcodes.h"
+#include "radeon_program.h"
+
+#include "radeon_program_constants.h"
 
 struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
        {
@@ -40,13 +43,15 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .Opcode = RC_OPCODE_ABS,
                .Name = "ABS",
                .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_ADD,
                .Name = "ADD",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_ARL,
@@ -54,29 +59,40 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .NumSrcRegs = 1,
                .HasDstReg = 1
        },
+       {
+               .Opcode = RC_OPCODE_CEIL,
+               .Name = "CEIL",
+               .NumSrcRegs = 1,
+               .HasDstReg = 1,
+               .IsComponentwise = 1
+       },
        {
                .Opcode = RC_OPCODE_CMP,
                .Name = "CMP",
                .NumSrcRegs = 3,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_COS,
                .Name = "COS",
                .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsStandardScalar = 1
        },
        {
                .Opcode = RC_OPCODE_DDX,
                .Name = "DDX",
-               .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .NumSrcRegs = 2,
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_DDY,
                .Name = "DDY",
-               .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .NumSrcRegs = 2,
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_DP3,
@@ -106,7 +122,8 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .Opcode = RC_OPCODE_EX2,
                .Name = "EX2",
                .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsStandardScalar = 1
        },
        {
                .Opcode = RC_OPCODE_EXP,
@@ -118,13 +135,15 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .Opcode = RC_OPCODE_FLR,
                .Name = "FLR",
                .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_FRC,
                .Name = "FRC",
                .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_KIL,
@@ -135,7 +154,8 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .Opcode = RC_OPCODE_LG2,
                .Name = "LG2",
                .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsStandardScalar = 1
        },
        {
                .Opcode = RC_OPCODE_LIT,
@@ -153,55 +173,64 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .Opcode = RC_OPCODE_LRP,
                .Name = "LRP",
                .NumSrcRegs = 3,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_MAD,
                .Name = "MAD",
                .NumSrcRegs = 3,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_MAX,
                .Name = "MAX",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_MIN,
                .Name = "MIN",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_MOV,
                .Name = "MOV",
                .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_MUL,
                .Name = "MUL",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_POW,
                .Name = "POW",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsStandardScalar = 1
        },
        {
                .Opcode = RC_OPCODE_RCP,
                .Name = "RCP",
                .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsStandardScalar = 1
        },
        {
                .Opcode = RC_OPCODE_RSQ,
                .Name = "RSQ",
                .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsStandardScalar = 1
        },
        {
                .Opcode = RC_OPCODE_SCS,
@@ -213,61 +242,71 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .Opcode = RC_OPCODE_SEQ,
                .Name = "SEQ",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_SFL,
                .Name = "SFL",
                .NumSrcRegs = 0,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_SGE,
                .Name = "SGE",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_SGT,
                .Name = "SGT",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_SIN,
                .Name = "SIN",
                .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsStandardScalar = 1
        },
        {
                .Opcode = RC_OPCODE_SLE,
                .Name = "SLE",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_SLT,
                .Name = "SLT",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_SNE,
                .Name = "SNE",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_SUB,
                .Name = "SUB",
                .NumSrcRegs = 2,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_SWZ,
                .Name = "SWZ",
                .NumSrcRegs = 1,
-               .HasDstReg = 1
+               .HasDstReg = 1,
+               .IsComponentwise = 1
        },
        {
                .Opcode = RC_OPCODE_XPD,
@@ -310,9 +349,134 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
                .NumSrcRegs = 1,
                .HasDstReg = 1
        },
+       {
+               .Opcode = RC_OPCODE_IF,
+               .Name = "IF",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 1
+       },
+       {
+               .Opcode = RC_OPCODE_ELSE,
+               .Name = "ELSE",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 0
+       },
+       {
+               .Opcode = RC_OPCODE_ENDIF,
+               .Name = "ENDIF",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 0
+       },
+       {
+               .Opcode = RC_OPCODE_BGNLOOP,
+               .Name = "BGNLOOP",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 0
+       },
+       {
+               .Opcode = RC_OPCODE_BRK,
+               .Name = "BRK",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 0
+       },
+       {
+               .Opcode = RC_OPCODE_ENDLOOP,
+               .Name = "ENDLOOP",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 0,
+       },
+       {
+               .Opcode = RC_OPCODE_CONTINUE,
+               .Name = "CONTINUE",
+               .IsFlowControl = 1,
+               .NumSrcRegs = 0
+       },
        {
                .Opcode = RC_OPCODE_REPL_ALPHA,
                .Name = "REPL_ALPHA",
                .HasDstReg = 1
+       },
+       {
+               .Opcode = RC_OPCODE_BEGIN_TEX,
+               .Name = "BEGIN_TEX"
+       },
+       {
+               .Opcode = RC_OPCODE_KILP,
+               .Name = "KILP",
        }
 };
+
+void rc_compute_sources_for_writemask(
+               const struct rc_instruction *inst,
+               unsigned int writemask,
+               unsigned int *srcmasks)
+{
+       const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
+       srcmasks[0] = 0;
+       srcmasks[1] = 0;
+       srcmasks[2] = 0;
+
+       if (opcode->Opcode == RC_OPCODE_KIL)
+               srcmasks[0] |= RC_MASK_XYZW;
+       else if (opcode->Opcode == RC_OPCODE_IF)
+               srcmasks[0] |= RC_MASK_X;
+
+       if (!writemask)
+               return;
+
+       if (opcode->IsComponentwise) {
+               for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src)
+                       srcmasks[src] |= writemask;
+       } else if (opcode->IsStandardScalar) {
+               for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src)
+                       srcmasks[src] |= RC_MASK_X;
+       } else {
+               switch(opcode->Opcode) {
+               case RC_OPCODE_ARL:
+                       srcmasks[0] |= RC_MASK_X;
+                       break;
+               case RC_OPCODE_DP3:
+                       srcmasks[0] |= RC_MASK_XYZ;
+                       srcmasks[1] |= RC_MASK_XYZ;
+                       break;
+               case RC_OPCODE_DP4:
+                       srcmasks[0] |= RC_MASK_XYZW;
+                       srcmasks[1] |= RC_MASK_XYZW;
+                       break;
+               case RC_OPCODE_TXB:
+               case RC_OPCODE_TXP:
+                       srcmasks[0] |= RC_MASK_W;
+                       /* Fall through */
+               case RC_OPCODE_TEX:
+                       switch (inst->U.I.TexSrcTarget) {
+                               case RC_TEXTURE_1D:
+                                       srcmasks[0] |= RC_MASK_X;
+                                       break;
+                               case RC_TEXTURE_2D:
+                               case RC_TEXTURE_RECT:
+                               case RC_TEXTURE_1D_ARRAY:
+                                       srcmasks[0] |= RC_MASK_XY;
+                                       break;
+                               case RC_TEXTURE_3D:
+                               case RC_TEXTURE_CUBE:
+                               case RC_TEXTURE_2D_ARRAY:
+                                       srcmasks[0] |= RC_MASK_XYZ;
+                                       break;
+                       }
+                       break;
+               case RC_OPCODE_DST:
+                       srcmasks[0] |= RC_MASK_Y | RC_MASK_Z;
+                       srcmasks[1] |= RC_MASK_Y | RC_MASK_W;
+                       break;
+               case RC_OPCODE_EXP:
+               case RC_OPCODE_LOG:
+                       srcmasks[0] |= RC_MASK_XY;
+                       break;
+               case RC_OPCODE_LIT:
+                       srcmasks[0] |= RC_MASK_X | RC_MASK_Y | RC_MASK_W;
+                       break;
+               default:
+                       break;
+               }
+       }
+}