#include "radeon_opcodes.h"
#include "radeon_code.h"
+#include "radeon_program_constants.h"
+#include "radeon_program_pair.h"
struct radeon_compiler;
-typedef enum {
- RC_SATURATE_NONE = 0,
- RC_SATURATE_ZERO_ONE,
- RC_SATURATE_MINUS_PLUS_ONE
-} rc_saturate_mode;
-
-typedef enum {
- RC_TEXTURE_2D_ARRAY,
- RC_TEXTURE_1D_ARRAY,
- RC_TEXTURE_CUBE,
- RC_TEXTURE_3D,
- RC_TEXTURE_RECT,
- RC_TEXTURE_2D,
- RC_TEXTURE_1D
-} rc_texture_target;
-
-typedef enum {
- /**
- * Used to indicate unused register descriptions and
- * source register that use a constant swizzle.
- */
- RC_FILE_NONE = 0,
- RC_FILE_TEMPORARY,
-
- /**
- * Input register.
- *
- * \note The compiler attaches no implicit semantics to input registers.
- * Fragment/vertex program specific semantics must be defined explicitly
- * using the appropriate compiler interfaces.
- */
- RC_FILE_INPUT,
-
- /**
- * Output register.
- *
- * \note The compiler attaches no implicit semantics to input registers.
- * Fragment/vertex program specific semantics must be defined explicitly
- * using the appropriate compiler interfaces.
- */
- RC_FILE_OUTPUT,
- RC_FILE_ADDRESS,
-
- /**
- * Indicates a constant from the \ref rc_constant_list .
- */
- RC_FILE_CONSTANT
-} rc_register_file;
-
-#define RC_REGISTER_INDEX_BITS 10
-#define RC_REGISTER_MAX_INDEX (1 << RC_REGISTER_INDEX_BITS)
-
-typedef enum {
- RC_SWIZZLE_X = 0,
- RC_SWIZZLE_Y,
- RC_SWIZZLE_Z,
- RC_SWIZZLE_W,
- RC_SWIZZLE_ZERO,
- RC_SWIZZLE_ONE,
- RC_SWIZZLE_HALF,
- RC_SWIZZLE_UNUSED
-} rc_swizzle;
-
-#define RC_MAKE_SWIZZLE(a,b,c,d) (((a)<<0) | ((b)<<3) | ((c)<<6) | ((d)<<9))
-#define RC_MAKE_SWIZZLE_SMEAR(a) RC_MAKE_SWIZZLE((a),(a),(a),(a))
-#define GET_SWZ(swz, idx) (((swz) >> ((idx)*3)) & 0x7)
-#define GET_BIT(msk, idx) (((msk) >> (idx)) & 0x1)
-
-#define RC_SWIZZLE_XYZW RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_W)
-#define RC_SWIZZLE_XXXX RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_X)
-#define RC_SWIZZLE_YYYY RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_Y)
-#define RC_SWIZZLE_ZZZZ RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_Z)
-#define RC_SWIZZLE_WWWW RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_W)
-#define RC_SWIZZLE_0000 RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_ZERO)
-#define RC_SWIZZLE_1111 RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_ONE)
-
-/**
- * \name Bitmasks for components of vectors.
- *
- * Used for write masks, negation masks, etc.
- */
-/*@{*/
-#define RC_MASK_NONE 0
-#define RC_MASK_X 1
-#define RC_MASK_Y 2
-#define RC_MASK_Z 4
-#define RC_MASK_W 8
-#define RC_MASK_XY (RC_MASK_X|RC_MASK_Y)
-#define RC_MASK_XYZ (RC_MASK_X|RC_MASK_Y|RC_MASK_Z)
-#define RC_MASK_XYW (RC_MASK_X|RC_MASK_Y|RC_MASK_W)
-#define RC_MASK_XYZW (RC_MASK_X|RC_MASK_Y|RC_MASK_Z|RC_MASK_W)
-/*@}*/
-
struct rc_src_register {
- rc_register_file File:3;
+ unsigned int File:3;
/** Negative values may be used for relative addressing. */
signed int Index:(RC_REGISTER_INDEX_BITS+1);
};
struct rc_dst_register {
- rc_register_file File:3;
+ unsigned int File:3;
/** Negative values may be used for relative addressing. */
signed int Index:(RC_REGISTER_INDEX_BITS+1);
* instruction types may be valid.
*/
struct rc_sub_instruction {
- struct rc_src_register SrcReg[3];
- struct rc_dst_register DstReg;
-
- /**
- * Opcode of this instruction, according to \ref rc_opcode enums.
- */
- rc_opcode Opcode:8;
-
- /**
- * Saturate each value of the result to the range [0,1] or [-1,1],
- * according to \ref rc_saturate_mode enums.
- */
- rc_saturate_mode SaturateMode:2;
-
- /**
- * \name Extra fields for TEX, TXB, TXD, TXL, TXP instructions.
- */
- /*@{*/
- /** Source texture unit. */
- unsigned int TexSrcUnit:5;
-
- /** Source texture target, one of the \ref rc_texture_target enums */
- rc_texture_target TexSrcTarget:3;
-
- /** True if tex instruction should do shadow comparison */
- unsigned int TexShadow:1;
- /*@}*/
+ struct rc_src_register SrcReg[3];
+ struct rc_dst_register DstReg;
+
+ /**
+ * Opcode of this instruction, according to \ref rc_opcode enums.
+ */
+ unsigned int Opcode:8;
+
+ /**
+ * Saturate each value of the result to the range [0,1] or [-1,1],
+ * according to \ref rc_saturate_mode enums.
+ */
+ unsigned int SaturateMode:2;
+
+ /**
+ * Writing to the special register RC_SPECIAL_ALU_RESULT
+ */
+ /*@{*/
+ unsigned int WriteALUResult:2;
+ unsigned int ALUResultCompare:3;
+ /*@}*/
+
+ /**
+ * \name Extra fields for TEX, TXB, TXD, TXL, TXP instructions.
+ */
+ /*@{*/
+ /** Source texture unit. */
+ unsigned int TexSrcUnit:5;
+
+ /** Source texture target, one of the \ref rc_texture_target enums */
+ unsigned int TexSrcTarget:3;
+
+ /** True if tex instruction should do shadow comparison */
+ unsigned int TexShadow:1;
+ /*@}*/
};
+typedef enum {
+ RC_INSTRUCTION_NORMAL = 0,
+ RC_INSTRUCTION_PAIR
+} rc_instruction_type;
+
struct rc_instruction {
struct rc_instruction * Prev;
struct rc_instruction * Next;
- struct rc_sub_instruction I;
+ rc_instruction_type Type;
+ union {
+ struct rc_sub_instruction I;
+ struct rc_pair_instruction P;
+ } U;
+
+ /**
+ * Warning: IPs are not stable. If you want to use them,
+ * you need to recompute them at the beginning of each pass
+ * using \ref rc_recompute_ips
+ */
+ unsigned int IP;
};
struct rc_program {
static inline void reset_srcreg(struct rc_src_register* reg)
{
- memset(reg, 0, sizeof(reg));
+ memset(reg, 0, sizeof(struct rc_src_register));
reg->Swizzle = RC_SWIZZLE_XYZW;
}
struct rc_instruction *rc_alloc_instruction(struct radeon_compiler * c);
struct rc_instruction *rc_insert_new_instruction(struct radeon_compiler * c, struct rc_instruction * after);
+void rc_insert_instruction(struct rc_instruction * after, struct rc_instruction * inst);
void rc_remove_instruction(struct rc_instruction * inst);
+unsigned int rc_recompute_ips(struct radeon_compiler * c);
+
void rc_print_program(const struct rc_program *prog);
#endif
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