r300/compiler: refactor vertex shader compilation

[mesa.git] / src / mesa / drivers / dri / r300 / compiler / radeon_program.h

diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program.h b/src/mesa/drivers/dri/r300/compiler/radeon_program.h
index d38c9a420c68f1d1b204b32864733d6c8eaf9b11..ee4fe8192e23a08636fabef81952418df6fead09 100644 (file)
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program.h
@@ -34,12 +34,12 @@
 #include "radeon_opcodes.h"
 #include "radeon_code.h"
 #include "radeon_program_constants.h"
-#include "radeon_dataflow.h"
+#include "radeon_program_pair.h"
 
 struct radeon_compiler;
 
 struct rc_src_register {
-       rc_register_file File:3;
+       unsigned int File:3;
 
        /** Negative values may be used for relative addressing. */
        signed int Index:(RC_REGISTER_INDEX_BITS+1);
@@ -55,7 +55,7 @@ struct rc_src_register {
 };
 
 struct rc_dst_register {
-       rc_register_file File:3;
+       unsigned int File:3;
 
        /** Negative values may be used for relative addressing. */
        signed int Index:(RC_REGISTER_INDEX_BITS+1);
@@ -73,49 +73,64 @@ struct rc_dst_register {
  * instruction types may be valid.
  */
 struct rc_sub_instruction {
-               struct rc_src_register SrcReg[3];
-               struct rc_dst_register DstReg;
-
-               /**
-                * Opcode of this instruction, according to \ref rc_opcode enums.
-                */
-               rc_opcode Opcode:8;
-
-               /**
-                * Saturate each value of the result to the range [0,1] or [-1,1],
-                * according to \ref rc_saturate_mode enums.
-                */
-               rc_saturate_mode SaturateMode:2;
-
-               /**
-                * \name Extra fields for TEX, TXB, TXD, TXL, TXP instructions.
-                */
-               /*@{*/
-               /** Source texture unit. */
-               unsigned int TexSrcUnit:5;
-
-               /** Source texture target, one of the \ref rc_texture_target enums */
-               rc_texture_target TexSrcTarget:3;
-
-               /** True if tex instruction should do shadow comparison */
-               unsigned int TexShadow:1;
-               /*@}*/
+       struct rc_src_register SrcReg[3];
+       struct rc_dst_register DstReg;
+
+       /**
+        * Opcode of this instruction, according to \ref rc_opcode enums.
+        */
+       unsigned int Opcode:8;
+
+       /**
+        * Saturate each value of the result to the range [0,1] or [-1,1],
+        * according to \ref rc_saturate_mode enums.
+        */
+       unsigned int SaturateMode:2;
+
+       /**
+        * Writing to the special register RC_SPECIAL_ALU_RESULT
+        */
+       /*@{*/
+       unsigned int WriteALUResult:2;
+       unsigned int ALUResultCompare:3;
+       /*@}*/
+
+       /**
+        * \name Extra fields for TEX, TXB, TXD, TXL, TXP instructions.
+        */
+       /*@{*/
+       /** Source texture unit. */
+       unsigned int TexSrcUnit:5;
+
+       /** Source texture target, one of the \ref rc_texture_target enums */
+       unsigned int TexSrcTarget:3;
+
+       /** True if tex instruction should do shadow comparison */
+       unsigned int TexShadow:1;
+       /*@}*/
 };
 
+typedef enum {
+       RC_INSTRUCTION_NORMAL = 0,
+       RC_INSTRUCTION_PAIR
+} rc_instruction_type;
+
 struct rc_instruction {
        struct rc_instruction * Prev;
        struct rc_instruction * Next;
 
-       struct rc_sub_instruction I;
+       rc_instruction_type Type;
+       union {
+               struct rc_sub_instruction I;
+               struct rc_pair_instruction P;
+       } U;
 
        /**
-        * Dataflow annotations.
-        *
-        * These are not supplied by the caller of the compiler,
-        * but filled in during compilation stages that make use of
-        * dataflow analysis.
+        * Warning: IPs are not stable. If you want to use them,
+        * you need to recompute them at the beginning of each pass
+        * using \ref rc_recompute_ips
         */
-       struct rc_instruction_dataflow Dataflow;
+       unsigned int IP;
 };
 
 struct rc_program {
@@ -176,13 +191,13 @@ struct rc_src_register lmul_swizzle(unsigned int swizzle, struct rc_src_register
 
 static inline void reset_srcreg(struct rc_src_register* reg)
 {
-       memset(reg, 0, sizeof(reg));
+       memset(reg, 0, sizeof(struct rc_src_register));
        reg->Swizzle = RC_SWIZZLE_XYZW;
 }
 
 
 /**
- * A transformation that can be passed to \ref radeonLocalTransform.
+ * A transformation that can be passed to \ref rc_local_transform.
  *
  * The function will be called once for each instruction.
  * It has to either emit the appropriate transformed code for the instruction
@@ -199,21 +214,19 @@ struct radeon_program_transformation {
        void *userData;
 };
 
-void radeonLocalTransform(
+void rc_local_transform(
        struct radeon_compiler *c,
-       int num_transformations,
-       struct radeon_program_transformation* transformations);
+       void *user);
 
 unsigned int rc_find_free_temporary(struct radeon_compiler * c);
 
 struct rc_instruction *rc_alloc_instruction(struct radeon_compiler * c);
 struct rc_instruction *rc_insert_new_instruction(struct radeon_compiler * c, struct rc_instruction * after);
+void rc_insert_instruction(struct rc_instruction * after, struct rc_instruction * inst);
 void rc_remove_instruction(struct rc_instruction * inst);
 
-enum {
-       RC_PRINT_DATAFLOW = 0x1
-};
+unsigned int rc_recompute_ips(struct radeon_compiler * c);
 
-void rc_print_program(const struct rc_program *prog, unsigned int flags);
+void rc_print_program(const struct rc_program *prog);
 
 #endif