r300: fix vertex program parameters limits

[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index b08af116a120c3f5a2ebb8f02f8981330f5ed287..0fe32a5443aeeb3885e6d6da9419979cf4f4bfaa 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -105,7 +105,7 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
        ndw -= 5;
        OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
        OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
-       OUT_BATCH_TABLE(atom->cmd + 1, ndw);
+       OUT_BATCH_TABLE(&atom->cmd[1], ndw);
        OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
        END_BATCH();
 }
@@ -134,7 +134,7 @@ void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
        OUT_BATCH(addr);
        ndw-=3;
        OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
-       OUT_BATCH_TABLE(atom->cmd + 1, ndw);
+       OUT_BATCH_TABLE(&atom->cmd[1], ndw);
        END_BATCH();
 }
 
@@ -226,8 +226,8 @@ void r300_emit_scissor(GLcontext *ctx)
     if (r300->radeon.state.scissor.enabled) {
         x1 = r300->radeon.state.scissor.rect.x1;
         y1 = r300->radeon.state.scissor.rect.y1;
-        x2 = r300->radeon.state.scissor.rect.x2 - 1;
-        y2 = r300->radeon.state.scissor.rect.y2 - 1;
+        x2 = r300->radeon.state.scissor.rect.x2;
+        y2 = r300->radeon.state.scissor.rect.y2;
     } else {
         x1 = 0;
         y1 = 0;
@@ -274,7 +274,7 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
                return;
        }
 
-        if (RADEON_DEBUG & DEBUG_STATE)
+        if (RADEON_DEBUG & RADEON_STATE)
            fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
        cbpitch = (rrb->pitch / rrb->cpp);
        if (rrb->cpp == 4)
@@ -494,7 +494,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
        r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
 
        mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
-       if (RADEON_DEBUG & DEBUG_TEXTURE) {
+       if (RADEON_DEBUG & RADEON_TEXTURE) {
                fprintf(stderr, "Using %d maximum texture units..\n", mtu);
        }
 
@@ -684,7 +684,11 @@ void r300InitCmdBuf(r300ContextPtr r300)
        r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
        ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
        r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
-       if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
+       if ((r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) ||
+             ( !r300->radeon.radeonScreen->kernel_mm && (
+           (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS400) ||
+           (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
+           (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420) ) ) ) {
                ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
        } else {
                ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);