r300: clear not_flushed OQ list after flush

[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 90ca45b3e77a6843c3d4f0ee564d411ba2c309c4..bd46f9acf2e64dd69cd5c9485695cd9243eaac74 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -164,47 +164,46 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
        r300ContextPtr r300 = R300_CONTEXT(ctx);
        BATCH_LOCALS(&r300->radeon);
        int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
-       int notexture = 0;
-
-       if (numtmus) {
-               int i;
-
-               for(i = 0; i < numtmus; ++i) {
-                   radeonTexObj *t = r300->hw.textures[i];
-
-                   if (!t)
-                       notexture = 1;
-               }
-
-               if (r300->radeon.radeonScreen->kernel_mm && notexture) {
-                       return;
-               }
-               for(i = 0; i < numtmus; ++i) {
-                   radeonTexObj *t = r300->hw.textures[i];
-                   if (t && !t->image_override) {
-                BEGIN_BATCH_NO_AUTOSTATE(4);
-                OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
-                           OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
-                                           RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-                END_BATCH();
-                   } else if (!t) {
-                /* Texture unit hasn't a texture bound nothings to do */
-                   } else { /* override cases */
-                           if (t->bo) {
-                    BEGIN_BATCH_NO_AUTOSTATE(4);
-                    OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
-                                   OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
-                                                   RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-                    END_BATCH();
-                           } else if (!r300->radeon.radeonScreen->kernel_mm) {
-                    BEGIN_BATCH_NO_AUTOSTATE(2);
-                    OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
-                                   OUT_BATCH(t->override_offset);
-                    END_BATCH();
-                           } else {
-                    /* Texture unit hasn't a texture bound nothings to do */
-                }
-                   }
+       int i;
+
+       for(i = 0; i < numtmus; ++i) {
+               radeonTexObj *t = r300->hw.textures[i];
+               if (t && !t->image_override) {
+                       BEGIN_BATCH_NO_AUTOSTATE(4);
+                       OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
+                       OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
+                                       RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+                       END_BATCH();
+               } else if (!t) {
+                       /* Texture unit hasn't a texture bound.
+                        * We assign the current color buffer as a fakery to make
+                        * KIL work on KMS (without it, the CS checker will complain).
+                        */
+                       if (r300->radeon.radeonScreen->kernel_mm) {
+                               struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
+                               if (rrb && rrb->bo) {
+                                       BEGIN_BATCH_NO_AUTOSTATE(4);
+                                       OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
+                                       OUT_BATCH_RELOC(0, rrb->bo, 0,
+                                                       RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+                                       END_BATCH();
+                               }
+                       }
+               } else { /* override cases */
+                       if (t->bo) {
+                               BEGIN_BATCH_NO_AUTOSTATE(4);
+                               OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
+                               OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
+                                               RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+                               END_BATCH();
+                       } else if (!r300->radeon.radeonScreen->kernel_mm) {
+                               BEGIN_BATCH_NO_AUTOSTATE(2);
+                               OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
+                               OUT_BATCH(t->override_offset);
+                               END_BATCH();
+                       } else {
+                               /* Texture unit hasn't a texture bound nothings to do */
+                       }
                }
        }
 }
@@ -269,8 +268,17 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
        cbpitch = (rrb->pitch / rrb->cpp);
        if (rrb->cpp == 4)
                cbpitch |= R300_COLOR_FORMAT_ARGB8888;
-       else
+       else switch (rrb->base._ActualFormat) {
+       case GL_RGB5:
                cbpitch |= R300_COLOR_FORMAT_RGB565;
+               break;
+       case GL_RGBA4:
+               cbpitch |= R300_COLOR_FORMAT_ARGB4444;
+               break;
+       case GL_RGB5_A1:
+               cbpitch |= R300_COLOR_FORMAT_ARGB1555;
+               break;
+       }
 
        if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
                cbpitch |= R300_COLOR_TILE_ENABLE;
@@ -335,23 +343,33 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
        BATCH_LOCALS(&r300->radeon);
        struct radeon_renderbuffer *rrb;
        uint32_t zbpitch;
+       uint32_t dw;
 
        rrb = radeon_get_depthbuffer(&r300->radeon);
        if (!rrb)
                return;
 
        zbpitch = (rrb->pitch / rrb->cpp);
-       if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
-               zbpitch |= R300_DEPTHMACROTILE_ENABLE;
-       }
-       if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
-               zbpitch |= R300_DEPTHMICROTILE_TILED;
+       if (!r300->radeon.radeonScreen->kernel_mm) {
+           if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
+               zbpitch |= R300_DEPTHMACROTILE_ENABLE;
+          }
+           if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
+               zbpitch |= R300_DEPTHMICROTILE_TILED;
+           }
        }
 
-       BEGIN_BATCH_NO_AUTOSTATE(6);
+       dw = 6;
+       if (r300->radeon.radeonScreen->kernel_mm)
+               dw += 2;
+       BEGIN_BATCH_NO_AUTOSTATE(dw);
        OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
        OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
-       OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
+       OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
+       if (!r300->radeon.radeonScreen->kernel_mm)
+           OUT_BATCH(zbpitch);
+       else
+           OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
        END_BATCH();
 }