Merge branch 'mesa_7_7_branch'
[mesa.git] / src / mesa / drivers / dri / r300 / r300_context.c
index ca8021df16a0243e317dd6d5ecdc367c48c2b08b..3c6ec2a34a8fc9f85fa338198e25904da1266021 100644 (file)
@@ -55,13 +55,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "tnl/t_vp_build.h"
 
 #include "drivers/common/driverfuncs.h"
+#include "drivers/common/meta.h"
 
 #include "r300_context.h"
 #include "radeon_context.h"
 #include "radeon_span.h"
+#include "r300_blit.h"
 #include "r300_cmdbuf.h"
 #include "r300_state.h"
-#include "r300_ioctl.h"
 #include "r300_tex.h"
 #include "r300_emit.h"
 #include "r300_swtcl.h"
@@ -80,18 +81,21 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define need_GL_EXT_blend_equation_separate
 #define need_GL_EXT_blend_func_separate
 #define need_GL_EXT_blend_minmax
+#define need_GL_EXT_framebuffer_blit
 #define need_GL_EXT_framebuffer_object
 #define need_GL_EXT_fog_coord
 #define need_GL_EXT_gpu_program_parameters
+#define need_GL_EXT_provoking_vertex
 #define need_GL_EXT_secondary_color
 #define need_GL_EXT_stencil_two_side
 #define need_GL_ATI_separate_stencil
 #define need_GL_NV_vertex_program
 
-#include "extension_helper.h"
+#include "main/remap_helper.h"
 
+void r300_init_texcopy_functions(struct dd_function_table *table);
 
-const struct dri_extension card_extensions[] = {
+static const struct dri_extension card_extensions[] = {
   /* *INDENT-OFF* */
   {"GL_ARB_depth_texture",             NULL},
   {"GL_ARB_fragment_program",          NULL},
@@ -115,6 +119,7 @@ const struct dri_extension card_extensions[] = {
   {"GL_EXT_packed_depth_stencil",      NULL},
   {"GL_EXT_fog_coord",                 GL_EXT_fog_coord_functions },
   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
+  {"GL_EXT_provoking_vertex",           GL_EXT_provoking_vertex_functions },
   {"GL_EXT_secondary_color",           GL_EXT_secondary_color_functions},
   {"GL_EXT_shadow_funcs",              NULL},
   {"GL_EXT_stencil_two_side",          GL_EXT_stencil_two_side_functions},
@@ -142,7 +147,8 @@ const struct dri_extension card_extensions[] = {
 };
 
 
-const struct dri_extension mm_extensions[] = {
+static const struct dri_extension mm_extensions[] = {
+  { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions },
   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
   { NULL, NULL }
 };
@@ -151,7 +157,7 @@ const struct dri_extension mm_extensions[] = {
  * The GL 2.0 functions are needed to make display lists work with
  * functions added by GL_ATI_separate_stencil.
  */
-const struct dri_extension gl_20_extension[] = {
+static const struct dri_extension gl_20_extension[] = {
   {"GL_VERSION_2_0",                   GL_VERSION_2_0_functions },
 };
 
@@ -212,11 +218,8 @@ static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes
 
 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 {
-       r300ContextPtr r300 = (r300ContextPtr)radeon;
        BATCH_LOCALS(radeon);
 
-       r300->vap_flush_needed = GL_TRUE;
-
        cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
        BEGIN_BATCH_NO_AUTOSTATE(2);
        OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
@@ -239,8 +242,8 @@ static void r300_emit_query_finish(radeonContextPtr radeon)
        struct radeon_query_object *query = radeon->query.current;
        BATCH_LOCALS(radeon);
 
-       BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->num_z_pipes + 2);
-       switch (r300->num_z_pipes) {
+       BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
+       switch (r300->radeon.radeonScreen->num_gb_pipes) {
        case 4:
                OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
                OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
@@ -266,7 +269,7 @@ static void r300_emit_query_finish(radeonContextPtr radeon)
        }
        OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
        END_BATCH();
-       query->curr_offset += r300->num_z_pipes * sizeof(uint32_t);
+       query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
        assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
        query->emitted_begin = GL_FALSE;
 }
@@ -288,14 +291,12 @@ static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
        query->emitted_begin = GL_FALSE;
 }
 
-#if 0
 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 {
-       r300ContextPtr r300 = (r300ContextPtr)radeon;
        BATCH_LOCALS(radeon);
        struct radeon_query_object *query = radeon->query.current;
 
-       BEGIN_BATCH_NO_AUTOSTATE(6);
+       BEGIN_BATCH_NO_AUTOSTATE(14);
        OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
        OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
        OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
@@ -309,7 +310,6 @@ static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
        assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
        query->emitted_begin = GL_FALSE;
 }
-#endif
 
 static void r300_init_vtbl(radeonContextPtr radeon)
 {
@@ -319,11 +319,12 @@ static void r300_init_vtbl(radeonContextPtr radeon)
        radeon->vtbl.swtcl_flush = r300_swtcl_flush;
        radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
        radeon->vtbl.fallback = r300_fallback;
-       if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530)
-               /* single Z gives me correct results on my hw need to check if we ever need
-                * double z */
-               radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
-       else
+       if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
+               if (radeon->radeonScreen->num_z_pipes == 2)
+                       radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
+               else
+                       radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
+       } else
                radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 }
 
@@ -366,13 +367,10 @@ static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
 
        /* currently bogus data */
        if (r300->options.hw_tcl_enabled) {
-               ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
-               ctx->Const.VertexProgram.MaxNativeInstructions =
-                 VSF_MAX_FRAGMENT_LENGTH / 4;
+               ctx->Const.VertexProgram.MaxNativeInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
+               ctx->Const.VertexProgram.MaxNativeAluInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
                ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
-               ctx->Const.VertexProgram.MaxTemps = 32;
-               ctx->Const.VertexProgram.MaxNativeTemps =
-                 /*VSF_MAX_FRAGMENT_TEMPS */ 32;
+               ctx->Const.VertexProgram.MaxNativeTemps = 32;
                ctx->Const.VertexProgram.MaxNativeParameters = 256;     /* r420 */
                ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
        }
@@ -380,11 +378,21 @@ static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
        if (screen->chip_family >= CHIP_FAMILY_RV515) {
                ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
                ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
-               ctx->Const.FragmentProgram.MaxNativeParameters = R500_PFS_NUM_CONST_REGS;
-               ctx->Const.FragmentProgram.MaxNativeAluInstructions = R500_PFS_MAX_INST;
-               ctx->Const.FragmentProgram.MaxNativeTexInstructions = R500_PFS_MAX_INST;
-               ctx->Const.FragmentProgram.MaxNativeInstructions = R500_PFS_MAX_INST;
-               ctx->Const.FragmentProgram.MaxNativeTexIndirections = R500_PFS_MAX_INST;
+
+               /* The hardware limits are higher than this,
+                * but the non-KMS DRM interface artificially limits us
+                * to this many instructions.
+                *
+                * We could of course work around it in the KMS path,
+                * but it would be a mess, so it seems wiser
+                * to leave it as is. Going forward, the Gallium driver
+                * will not be subject to these limitations.
+                */
+               ctx->Const.FragmentProgram.MaxNativeParameters = 255;
+               ctx->Const.FragmentProgram.MaxNativeAluInstructions = 255;
+               ctx->Const.FragmentProgram.MaxNativeTexInstructions = 255;
+               ctx->Const.FragmentProgram.MaxNativeInstructions = 255;
+               ctx->Const.FragmentProgram.MaxNativeTexIndirections = 255;
                ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
        } else {
                ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
@@ -397,10 +405,6 @@ static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
                ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
        }
 
-       if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530)
-               r300->num_z_pipes = 2;
-       else
-               r300->num_z_pipes = r300->radeon.radeonScreen->num_gb_pipes;
 }
 
 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
@@ -437,11 +441,11 @@ static void r300InitGLExtensions(GLcontext *ctx)
        if (r300->options.stencil_two_side_disabled)
                _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 
-       if (ctx->Mesa_DXTn && !r300->options.s3tc_force_enabled) {
+       if (r300->options.s3tc_force_disabled) {
+               _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
+       } else if (ctx->Mesa_DXTn || r300->options.s3tc_force_enabled) {
                _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
                _mesa_enable_extension(ctx, "GL_S3_s3tc");
-       } else if (r300->options.s3tc_force_disabled) {
-               _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
        }
 
        if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
@@ -449,6 +453,13 @@ static void r300InitGLExtensions(GLcontext *ctx)
        }
 }
 
+static void r300InitIoctlFuncs(struct dd_function_table *functions)
+{
+       functions->Clear = _mesa_meta_Clear;
+       functions->Finish = radeonFinish;
+       functions->Flush = radeonFlush;
+}
+
 /* Create the device specific rendering context.
  */
 GLboolean r300CreateContext(const __GLcontextModes * glVisual,
@@ -482,6 +493,10 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
        radeonInitQueryObjFunctions(&functions);
        radeonInitBufferObjectFuncs(&functions);
 
+       if (r300->radeon.radeonScreen->kernel_mm) {
+               r300_init_texcopy_functions(&functions);
+       }
+
        if (!radeonInitContext(&r300->radeon, &functions,
                               glVisual, driContextPriv,
                               sharedContextPrivate)) {
@@ -528,6 +543,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
                r300InitSwtcl(ctx);
        }
 
+       r300_blit_init(r300);
        radeon_fbo_init(&r300->radeon);
        radeonInitSpanFuncs( ctx );
        r300InitCmdBuf(r300);