#include "tnl/t_context.h"
#include "r300_context.h"
-#include "radeon_ioctl.h"
#include "r300_state.h"
#include "r300_emit.h"
#include "r300_ioctl.h"
GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead)
{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
GLuint i, vic_1 = 0;
if (InputsRead & (1 << VERT_ATTRIB_POS))
if (InputsRead & (1 << VERT_ATTRIB_COLOR0))
vic_1 |= R300_INPUT_CNTL_COLOR;
- rmesa->state.texture.tc_count = 0;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) {
- rmesa->state.texture.tc_count++;
vic_1 |= R300_INPUT_CNTL_TC0 << i;
}
GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten)
{
- GLuint i, ret = 0;
+ GLuint i, ret = 0, first_free_texcoord = 0;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
if (OutputsWritten & (1 << (VERT_RESULT_TEX0 + i))) {
ret |= (4 << (3 * i));
+ ++first_free_texcoord;
+ }
+ }
+
+ if (OutputsWritten & (1 << VERT_RESULT_FOGC)) {
+ if (first_free_texcoord > 8) {
+ fprintf(stderr, "\tout of free texcoords to write fog coord\n");
+ _mesa_exit(-1);
}
+ ret |= 1 << (3 * first_free_texcoord);
}
return ret;
struct r300_vertex_program *prog =
(struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
- if (hw_tcl_on) {
+ if (rmesa->options.hw_tcl_enabled) {
inputs = prog->inputs;
InputsRead = prog->key.InputsRead;
OutputsWritten = prog->key.OutputsWritten;
} else {
- inputs = rmesa->state.sw_tcl_inputs;
+ inputs = rmesa->swtcl.sw_tcl_inputs;
DECLARE_RENDERINPUTS(render_inputs_bitset);
RENDERINPUTS_COPY(render_inputs_bitset, tnl->render_inputs_bitset);
if (InputsRead & (1 << i))
inputs[i] = 6 + (i - VERT_ATTRIB_TEX0);
- RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, render_inputs_bitset);
+ RENDERINPUTS_COPY(rmesa->render_inputs_bitset, render_inputs_bitset);
}
assert(InputsRead);
for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) {
swizzle[i][ci] = ci;
}
- rcommon_emit_vector(ctx, &rmesa->state.aos[i],
+ rcommon_emit_vector(ctx, &rmesa->radeon.tcl.aos[i],
vb->AttribPtr[tab[i]]->data,
vb->AttribPtr[tab[i]]->size,
vb->AttribPtr[tab[i]]->stride, count);
r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle,
nr);
}
-
+
/* Setup INPUT_CNTL. */
R300_STATECHANGE(rmesa, vic);
rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead);
rmesa->hw.vof.cmd[R300_VOF_CNTL_1] =
r300VAPOutputCntl1(ctx, OutputsWritten);
- rmesa->state.aos_count = nr;
+ rmesa->radeon.tcl.aos_count = nr;
return R300_FALLBACK_NONE;
}
-void r300ReleaseArrays(GLcontext * ctx)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- int i;
-
- if (rmesa->state.elt_dma_bo) {
- radeon_bo_unref(rmesa->state.elt_dma_bo);
- rmesa->state.elt_dma_bo = NULL;
- }
- for (i = 0; i < rmesa->state.aos_count; i++) {
- if (rmesa->state.aos[i].bo) {
- radeon_bo_unref(rmesa->state.aos[i].bo);
- rmesa->state.aos[i].bo = NULL;
- }
- }
-}
-
void r300EmitCacheFlush(r300ContextPtr rmesa)
{
BATCH_LOCALS(&rmesa->radeon);
- BEGIN_BATCH(4);
+ BEGIN_BATCH_NO_AUTOSTATE(4);
OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT,
R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);