}
}
-static GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
+#define DW_SIZE(x) ((inputs[tab[(x)]] << R300_DST_VEC_LOC_SHIFT) | \
+ (attribptr[tab[(x)]]->size - 1) << R300_DATA_TYPE_0_SHIFT)
+
+GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
int *inputs, GLint * tab, GLuint nr)
{
GLuint i, dw;
for (i = 0; i < nr; i += 2) {
/* make sure input is valid, would lockup the gpu */
assert(inputs[tab[i]] != -1);
- dw = (R300_SIGNED |
- (inputs[tab[i]] << R300_DST_VEC_LOC_SHIFT) |
- (attribptr[tab[i]]->size - 1)) << R300_DATA_TYPE_0_SHIFT;
+ dw = (R300_SIGNED | DW_SIZE(i));
if (i + 1 == nr) {
dw |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT;
} else {
assert(inputs[tab[i + 1]] != -1);
dw |= (R300_SIGNED |
- (inputs[tab[i + 1]] << R300_DST_VEC_LOC_SHIFT) |
- (attribptr[tab[i + 1]]->size - 1)) << R300_DATA_TYPE_1_SHIFT;
+ DW_SIZE(i + 1)) << R300_DATA_TYPE_1_SHIFT;
if (i + 2 == nr) {
dw |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT;
}
drm_radeon_cmd_header_t *cmd = NULL;
reg_start(R300_RB3D_DSTCACHE_CTLSTAT, 0);
- e32(RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
- RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
+ e32(R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
+ R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
- reg_start(ZB_ZCACHE_CTLSTAT, 0);
- e32(ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
- ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
+ reg_start(R300_ZB_ZCACHE_CTLSTAT, 0);
+ e32(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
+ R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
}