if (!rscrn->kernel_mm) {
drm_r300_cmd_header_t cmd;
+ cmd.u = 0;
cmd.packet0.cmd_type = R300_CMD_PACKET0;
cmd.packet0.count = count;
cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8;
{
drm_r300_cmd_header_t cmd;
+ cmd.u = 0;
cmd.vpu.cmd_type = R300_CMD_VPU;
cmd.vpu.count = count;
cmd.vpu.adrhi = ((unsigned int)addr & 0xFF00) >> 8;
{
drm_r300_cmd_header_t cmd;
+ cmd.u = 0;
cmd.r500fp.cmd_type = R300_CMD_R500FP;
cmd.r500fp.count = count;
cmd.r500fp.adrhi_flags = ((unsigned int)addr & 0x100) >> 8;
{
drm_r300_cmd_header_t cmd;
+ cmd.u = 0;
cmd.packet3.cmd_type = R300_CMD_PACKET3;
cmd.packet3.packet = packet;
return cmd.u;
}
-static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn,
+static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn,
unsigned short count)
{
drm_r300_cmd_header_t cmd;
+ cmd.u = 0;
+
cmd.delay.cmd_type = R300_CMD_CP_DELAY;
cmd.delay.count = count;
{
drm_r300_cmd_header_t cmd;
+ cmd.u = 0;
cmd.wait.cmd_type = R300_CMD_WAIT;
cmd.wait.flags = flags;
{
drm_r300_cmd_header_t cmd;
+ cmd.u = 0;
cmd.header.cmd_type = R300_CMD_END3D;
return cmd.u;
}
}
-extern int r300EmitArrays(GLcontext * ctx);
-
-extern void r300ReleaseArrays(GLcontext * ctx);
extern int r300PrimitiveType(r300ContextPtr rmesa, int prim);
extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
extern void r300EmitCacheFlush(r300ContextPtr rmesa);
-extern GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
- int *inputs, GLint * tab, GLuint nr);
-extern GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr);
extern GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead);
extern GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead);
-extern GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten);
-extern GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten);
+extern GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint vp_writes);
+extern GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint vp_writes);
#endif