#define CLEARBUFFER_COLOR 0x1
#define CLEARBUFFER_DEPTH 0x2
+#define CLEARBUFFER_STENCIL 0x4
static void r300ClearBuffer(r300ContextPtr r300, int flags, int buffer)
{
R300_STATECHANGE(r300, zs);
if (flags & CLEARBUFFER_DEPTH) {
- r300->hw.zs.cmd[R300_ZS_CNTL_0] = 0x6; // test and write
- r300->hw.zs.cmd[R300_ZS_CNTL_1] = (R300_ZS_ALWAYS<<R300_RB3D_ZS1_DEPTH_FUNC_SHIFT);
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] &= R300_RB3D_STENCIL_ENABLE;
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] |= 0x6; // test and write
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] &= ~(R300_ZS_MASK << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT);
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] |= (R300_ZS_ALWAYS<<R300_RB3D_ZS1_DEPTH_FUNC_SHIFT);
/*
R300_STATECHANGE(r300, zb);
r300->hw.zb.cmd[R300_ZB_OFFSET] =
r300->radeon.radeonScreen->depthPitch;
*/
} else {
- r300->hw.zs.cmd[R300_ZS_CNTL_0] = 0; // disable
- r300->hw.zs.cmd[R300_ZS_CNTL_1] = 0;
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] &= R300_RB3D_STENCIL_ENABLE;
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_RB3D_Z_DISABLED_1; // disable
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] &= ~(R300_ZS_MASK << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT);
+ }
+
+ R300_STATECHANGE(r300, zs);
+ if (flags & CLEARBUFFER_STENCIL) {
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] &= ~R300_RB3D_STENCIL_ENABLE;
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_RB3D_STENCIL_ENABLE;
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] &=
+ ~((R300_ZS_MASK << R300_RB3D_ZS1_FRONT_FUNC_SHIFT) | (R300_ZS_MASK << R300_RB3D_ZS1_BACK_FUNC_SHIFT));
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] |=
+ (R300_ZS_ALWAYS<<R300_RB3D_ZS1_FRONT_FUNC_SHIFT) |
+ (R300_ZS_REPLACE<<R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT) |
+ (R300_ZS_REPLACE<<R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT) |
+ (R300_ZS_REPLACE<<R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT) |
+ (R300_ZS_ALWAYS<<R300_RB3D_ZS1_BACK_FUNC_SHIFT) |
+ (R300_ZS_REPLACE<<R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT) |
+ (R300_ZS_REPLACE<<R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT) |
+ (R300_ZS_REPLACE<<R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT) ;
+ r300->hw.zs.cmd[R300_ZS_CNTL_2] = r300->state.stencil.clear;
}
/* Make sure we have enough space */
bits |= CLEARBUFFER_DEPTH;
mask &= ~DD_DEPTH_BIT;
}
+
+ if ( (mask & DD_STENCIL_BIT) && r300->state.stencil.hw_stencil) {
+ bits |= CLEARBUFFER_STENCIL;
+ mask &= ~DD_STENCIL_BIT;
+ }
if (mask) {
if (RADEON_DEBUG & DEBUG_FALLBACKS)
void r300RefillCurrentDmaRegion(r300ContextPtr rmesa)
{
- struct r200_dma_buffer *dmabuf;
+ struct r300_dma_buffer *dmabuf;
int fd = rmesa->radeon.dri.fd;
int index = 0;
int size = 0;
drmDMAReq dma;
int ret;
-
+
if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA))
fprintf(stderr, "%s\n", __FUNCTION__);
LOCK_HARDWARE(&rmesa->radeon); /* no need to validate */
- while (1) {
- ret = drmDMA(fd, &dma);
- if (ret == 0)
- break;
+ ret = drmDMA(fd, &dma);
+ if (ret != 0) {
+ /* Try to release some buffers and wait until we can't get any more */
if (rmesa->dma.nr_released_bufs) {
r300FlushCmdBufLocked(rmesa, __FUNCTION__);
}
- if (rmesa->radeon.do_usleeps) {
+ if (RADEON_DEBUG & DEBUG_DMA)
+ fprintf(stderr, "Waiting for buffers\n");
+
+ radeonWaitForIdleLocked(&rmesa->radeon);
+ ret = drmDMA(fd, &dma);
+
+ if (ret != 0) {
UNLOCK_HARDWARE(&rmesa->radeon);
- DO_USLEEP(1);
- LOCK_HARDWARE(&rmesa->radeon);
+ fprintf(stderr, "Error: Could not get dma buffer... exiting\n");
+ exit(-1);
}
}
if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA))
fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__,
region->buf->buf->idx);
-
cmd =
(drm_radeon_cmd_header_t *) r300AllocCmdBuf(rmesa,
- sizeof(*cmd),
+ sizeof(*cmd) / 4,
__FUNCTION__);
- cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD;
+ cmd->dma.cmd_type = R300_CMD_DMA_DISCARD;
cmd->dma.buf_idx = region->buf->buf->idx;
+
FREE(region->buf);
rmesa->dma.nr_released_bufs++;
}