Track Radeon driver symlinks in Git.

[mesa.git] / src / mesa / drivers / dri / r300 / r300_reg.h

diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index 872a33e258bd058ef9d6a7839e850c5f3193a5dd..357c600af974ce87852db6cae3a253ba1a76ed78 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -1224,6 +1224,10 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R500_RS_INST_COL_ADDR_SHIFT                    18
 #define R500_RS_INST_TEX_ADJ                           (1 << 25)
 #define R500_RS_INST_W_CN                              (1 << 26)
+#define R500_RS_INST_TEX_ID(x)                         ((x) << R500_RS_INST_TEX_ID_SHIFT)
+#define R500_RS_INST_TEX_ADDR(x)                       ((x) << R500_RS_INST_TEX_ADDR_SHIFT)
+#define R500_RS_INST_COL_ID(x)                         ((x) << R500_RS_INST_COL_ID_SHIFT)
+#define R500_RS_INST_COL_ADDR(x)                       ((x) << R500_RS_INST_COL_ADDR_SHIFT)
 
 /* These DWORDs control how vertex data is routed into fragment program
  * registers, after interpolators.
@@ -1239,9 +1243,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #      define R300_RS_INST_TEX_ID(x)           ((x) << 0)
 #      define R300_RS_INST_TEX_CN_WRITE        (1 << 3)
 #      define R300_RS_INST_TEX_ADDR_SHIFT      6
+#      define R300_RS_INST_TEX_ADDR(x)         ((x) << R300_RS_INST_TEX_ADDR_SHIFT)
 #      define R300_RS_INST_COL_ID(x)           ((x) << 11)
 #      define R300_RS_INST_COL_CN_WRITE        (1 << 14)
 #      define R300_RS_INST_COL_ADDR_SHIFT      17
+#      define R300_RS_INST_COL_ADDR(x)         ((x) << R300_RS_INST_COL_ADDR_SHIFT)
 #      define R300_RS_INST_TEX_ADJ             (1 << 22)
 #      define R300_RS_COL_BIAS_UNUSED_SHIFT    23
 
@@ -1461,6 +1467,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #      define R300_TX_FORMAT_3D                   (1 << 25)
 #      define R300_TX_FORMAT_CUBIC_MAP            (2 << 25)
 
+#      define R300_TX_FORMAT_GAMMA                     (1 << 21)
+
        /* gap */
        /* Floating point formats */
        /* Note - hardware supports both 16 and 32 bit floating point */
@@ -1525,6 +1533,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #      define R500_SEL_FILTER4_TC3              (3 << 18)
 
 #define R300_TX_OFFSET_0                    0x4540
+#define R300_TX_OFFSET_1                    0x4544
+#define R300_TX_OFFSET_2                    0x4548
+#define R300_TX_OFFSET_3                    0x454C
+#define R300_TX_OFFSET_4                    0x4550
+#define R300_TX_OFFSET_5                    0x4554
+#define R300_TX_OFFSET_6                    0x4558
+#define R300_TX_OFFSET_7                    0x455C
        /* BEGIN: Guess from R200 */
 #       define R300_TXO_ENDIAN_NO_SWAP           (0 << 0)
 #       define R300_TXO_ENDIAN_BYTE_SWAP         (1 << 0)
@@ -2419,6 +2434,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 /* Z Buffer Clear Value */
 #define R300_ZB_DEPTHCLEARVALUE                  0x4f28
 
+#define R300_ZB_ZMASK_OFFSET                     0x4f30
+#define R300_ZB_ZMASK_PITCH                      0x4f34
+#define R300_ZB_ZMASK_WRINDEX                    0x4f38
+#define R300_ZB_ZMASK_DWORD                      0x4f3c
+#define R300_ZB_ZMASK_RDINDEX                    0x4f40
+
 /* Hierarchical Z Memory Offset */
 #define R300_ZB_HIZ_OFFSET                       0x4f44
 
@@ -3159,6 +3180,9 @@ enum {
 #   define R300_W_SRC_RAS                              (1 << 2)
 
 
+/* Packet0 field ordering to write all values to the same reg */
+#define RADEON_ONE_REG_WR        (1 << 15)
+
 /* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
  * Two parameter dwords:
  * 0. VAP_VTX_FMT: The first parameter is not written to hardware