Merge branch 'mesa_7_6_branch'

[mesa.git] / src / mesa / drivers / dri / r300 / r300_reg.h

diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index ed552d09bbc6b765de201866140e7c1a1a021607..623da60333f2c8cf153286c490e3626514ee24d8 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -1022,15 +1022,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
        R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD | \
        R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \
        R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD | \
-       R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \
-       R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST )
+       R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD)
 /** TODO: might be candidate for removal, the GOURAUD stuff also looks buggy to me */
 #      define R300_RE_SHADE_MODEL_FLAT     ( \
        R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT | \
        R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \
        R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT | \
-       R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \
-       R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST )
+       R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD)
 
 /* Specifies red & green components of fill color -- S312 format -- Backwards comp. */
 #define R300_GA_SOLID_RG                         0x427c
@@ -1128,6 +1126,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 /* SU Depth Offset value */
 #define R300_SU_DEPTH_OFFSET                0x42c4
 
+#define R300_SU_REG_DEST                   0x42c8
+#      define R300_RASTER_PIPE_SELECT_0        (1 << 0)
+#      define R300_RASTER_PIPE_SELECT_1        (1 << 1)
+#      define R300_RASTER_PIPE_SELECT_2        (1 << 2)
+#      define R300_RASTER_PIPE_SELECT_3        (1 << 3)
+#      define R300_RASTER_PIPE_SELECT_ALL      0xf
+
 
 /* BEGIN: Rasterization / Interpolators - many guesses */
 
@@ -1467,6 +1472,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #      define R300_TX_FORMAT_3D                   (1 << 25)
 #      define R300_TX_FORMAT_CUBIC_MAP            (2 << 25)
 
+#      define R300_TX_FORMAT_GAMMA                     (1 << 21)
+
        /* gap */
        /* Floating point formats */
        /* Note - hardware supports both 16 and 32 bit floating point */
@@ -2012,6 +2019,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R500_FG_ALPHA_VALUE                0x4be0
 #      define R500_FG_ALPHA_VALUE_MASK 0x0000ffff
 
+#define RV530_FG_ZBREG_DEST                 0x4be8
+#      define RV530_FG_ZBREG_DEST_PIPE_SELECT_0             (1 << 0)
+#      define RV530_FG_ZBREG_DEST_PIPE_SELECT_1             (1 << 1)
+#      define RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL           (3 << 0)
+
 /* gap */
 
 /* Fragment program parameters in 7.16 floating point */
@@ -2301,6 +2313,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #      define R300_Z_WRITE_ENABLE               (1 << 2)
 #      define R300_Z_SIGNED_COMPARE             (1 << 3)
 #      define R300_STENCIL_FRONT_BACK           (1 << 4)
+#      define R400_ZSIGNED_MAGNITUDE            (1 << 5)
+#      define R500_STENCIL_REFMASK_FRONT_BACK   (1 << 6)
 
 #define R300_ZB_ZSTENCILCNTL                   0x4f04
        /* functions */
@@ -2432,6 +2446,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 /* Z Buffer Clear Value */
 #define R300_ZB_DEPTHCLEARVALUE                  0x4f28
 
+#define R300_ZB_ZMASK_OFFSET                     0x4f30
+#define R300_ZB_ZMASK_PITCH                      0x4f34
+#define R300_ZB_ZMASK_WRINDEX                    0x4f38
+#define R300_ZB_ZMASK_DWORD                      0x4f3c
+#define R300_ZB_ZMASK_RDINDEX                    0x4f40
+
 /* Hierarchical Z Memory Offset */
 #define R300_ZB_HIZ_OFFSET                       0x4f44
 
@@ -2659,6 +2679,24 @@ enum {
        PVS_SRC_ADDR_MODE_1_SHIFT       = 32,
 };
 
+
+#define PVS_OP_DST_OPERAND(opcode, math_inst, macro_inst, reg_index, reg_writemask, reg_class) \
+        (((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT)      \
+        | ((math_inst & PVS_DST_MATH_INST_MASK) << PVS_DST_MATH_INST_SHIFT)    \
+        | ((macro_inst & PVS_DST_MACRO_INST_MASK) << PVS_DST_MACRO_INST_SHIFT) \
+        | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT)  \
+        | ((reg_writemask & 0xf) << PVS_DST_WE_X_SHIFT)        /* X Y Z W */   \
+        | ((reg_class & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT))
+
+#define PVS_SRC_OPERAND(in_reg_index, comp_x, comp_y, comp_z, comp_w, reg_class, negate)       \
+       (((in_reg_index & PVS_SRC_OFFSET_MASK) << PVS_SRC_OFFSET_SHIFT)                         \
+        | ((comp_x & PVS_SRC_SWIZZLE_X_MASK) << PVS_SRC_SWIZZLE_X_SHIFT)                       \
+        | ((comp_y & PVS_SRC_SWIZZLE_Y_MASK) << PVS_SRC_SWIZZLE_Y_SHIFT)                       \
+        | ((comp_z & PVS_SRC_SWIZZLE_Z_MASK) << PVS_SRC_SWIZZLE_Z_SHIFT)                       \
+        | ((comp_w & PVS_SRC_SWIZZLE_W_MASK) << PVS_SRC_SWIZZLE_W_SHIFT)                       \
+        | ((negate & 0xf) << PVS_SRC_MODIFIER_X_SHIFT) /* X Y Z W */                           \
+        | ((reg_class & PVS_SRC_REG_TYPE_MASK) << PVS_SRC_REG_TYPE_SHIFT))
+
 /*\}*/
 
 /* BEGIN: Packet 3 commands */
@@ -2964,6 +3002,8 @@ enum {
 #   define R500_INST_RGB_CLAMP                         (1 << 19)
 #   define R500_INST_ALPHA_CLAMP                       (1 << 20)
 #   define R500_INST_ALU_RESULT_SEL                    (1 << 21)
+#   define R500_INST_ALU_RESULT_SEL_RED                (0 << 21)
+#   define R500_INST_ALU_RESULT_SEL_ALPHA              (1 << 21)
 #   define R500_INST_ALPHA_PRED_INV                    (1 << 22)
 #   define R500_INST_ALU_RESULT_OP_EQ                  (0 << 23)
 #   define R500_INST_ALU_RESULT_OP_LT                  (1 << 23)
@@ -3172,6 +3212,9 @@ enum {
 #   define R300_W_SRC_RAS                              (1 << 2)
 
 
+/* Packet0 field ordering to write all values to the same reg */
+#define RADEON_ONE_REG_WR        (1 << 15)
+
 /* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
  * Two parameter dwords:
  * 0. VAP_VTX_FMT: The first parameter is not written to hardware