radeon: make DRI1 one work with new CS mechanism
[mesa.git] / src / mesa / drivers / dri / r300 / r300_render.c
index f281e28e42718d1eac1068d9e02553098d41de15..dd9da80fd01d8fda334203b2ae6890c99dd38678 100644 (file)
@@ -199,11 +199,13 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
                   type |
                   R300_VAP_VF_CNTL__INDEX_SIZE_32bit);
 
-    if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) {
+    if (!rmesa->radeon.radeonScreen->kernel_mm) {
        OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
            OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2);
-       OUT_BATCH_RELOC(0, rmesa->state.elt_dma_bo,
-                        rmesa->state.elt_dma_offset, 0);
+       OUT_BATCH_RELOC(rmesa->state.elt_dma_offset,
+                        rmesa->state.elt_dma_bo,
+                        rmesa->state.elt_dma_offset,
+                        RADEON_GEM_DOMAIN_GTT, 0, 0);
         OUT_BATCH(vertex_count);
     } else {
        OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
@@ -214,7 +216,7 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
                               rmesa->state.elt_dma_bo,
                               0,
                               rmesa->state.elt_dma_bo->size,
-                              0);
+                              RADEON_GEM_DOMAIN_GTT, 0, 0);
     }
        END_BATCH();
     }
@@ -236,7 +238,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
        OUT_BATCH(nr);
 
     
-    if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) {
+    if (!rmesa->radeon.radeonScreen->kernel_mm) {
        for (i = 0; i + 1 < nr; i += 2) {
                OUT_BATCH((rmesa->state.aos[i].components << 0) |
                          (rmesa->state.aos[i].stride << 8) |
@@ -245,17 +247,30 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
 
         voffset =  rmesa->state.aos[i + 0].offset +
                    offset * 4 * rmesa->state.aos[i + 0].stride;
-               OUT_BATCH_RELOC(0, rmesa->state.aos[i].bo, voffset, 0);
+               OUT_BATCH_RELOC(voffset,
+                        rmesa->state.aos[i].bo,
+                        voffset,
+                        RADEON_GEM_DOMAIN_GTT,
+                        0, 0);
         voffset =  rmesa->state.aos[i + 1].offset +
                    offset * 4 * rmesa->state.aos[i + 1].stride;
-               OUT_BATCH_RELOC(0, rmesa->state.aos[i+1].bo, voffset, 0);
+               OUT_BATCH_RELOC(voffset,
+                        rmesa->state.aos[i+1].bo,
+                        voffset,
+                        RADEON_GEM_DOMAIN_GTT,
+                        0, 0);
        }
 
        if (nr & 1) {
                OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) |
                          (rmesa->state.aos[nr - 1].stride << 8));
-               OUT_BATCH_RELOC(0, rmesa->state.aos[nr - 1].bo,
-                       rmesa->state.aos[nr - 1].offset + offset * 4 * rmesa->state.aos[nr - 1].stride, 0);
+        voffset =  rmesa->state.aos[nr - 1].offset +
+                   offset * 4 * rmesa->state.aos[nr - 1].stride;
+               OUT_BATCH_RELOC(voffset,
+                        rmesa->state.aos[nr - 1].bo,
+                                   voffset,
+                        RADEON_GEM_DOMAIN_GTT,
+                        0, 0);
        }
     } else {
        for (i = 0; i + 1 < nr; i += 2) {
@@ -275,32 +290,37 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
        if (nr & 1) {
                OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) |
                          (rmesa->state.aos[nr - 1].stride << 8));
-               OUT_BATCH(rmesa->state.aos[nr - 1].offset + offset * 4 *
-                  rmesa->state.aos[nr - 1].stride);
+        voffset =  rmesa->state.aos[nr - 1].offset +
+                   offset * 4 * rmesa->state.aos[nr - 1].stride;
+               OUT_BATCH(voffset);
        }
        for (i = 0; i + 1 < nr; i += 2) {
-   #if 0
-        fprintf(stderr, "3D_LOAD_VBPNTR 0x%08X & 0x%08X\n",
-                rmesa->state.aos[i+0].bo->handle,
-                rmesa->state.aos[i+1].bo->handle);
-   #endif
+        voffset =  rmesa->state.aos[i + 0].offset +
+                   offset * 4 * rmesa->state.aos[i + 0].stride;
         radeon_cs_write_reloc(rmesa->cmdbuf.cs,
                               rmesa->state.aos[i+0].bo,
-                              0,
+                              voffset,
                               rmesa->state.aos[i+0].bo->size,
-                              0);
+                              RADEON_GEM_DOMAIN_GTT,
+                              0, 0);
+        voffset =  rmesa->state.aos[i + 1].offset +
+                   offset * 4 * rmesa->state.aos[i + 1].stride;
         radeon_cs_write_reloc(rmesa->cmdbuf.cs,
                               rmesa->state.aos[i+1].bo,
-                              0,
+                              voffset,
                               rmesa->state.aos[i+1].bo->size,
-                              0);
+                              RADEON_GEM_DOMAIN_GTT,
+                              0, 0);
        }
        if (nr & 1) {
+        voffset =  rmesa->state.aos[nr - 1].offset +
+                   offset * 4 * rmesa->state.aos[nr - 1].stride;
         radeon_cs_write_reloc(rmesa->cmdbuf.cs,
                               rmesa->state.aos[nr-1].bo,
-                              0,
+                              voffset,
                               rmesa->state.aos[nr-1].bo->size,
-                              0);
+                              RADEON_GEM_DOMAIN_GTT,
+                              0, 0);
        }
     }
        END_BATCH();