r300SetBlendState(ctx);
}
+static void r300ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
+{
+ r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ GLint p;
+ GLint *ip;
+
+ /* no VAP UCP on non-TCL chipsets */
+ if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
+ return;
+
+ p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
+ ip = (GLint *)ctx->Transform._ClipUserPlane[p];
+
+ R300_STATECHANGE( rmesa, vpucp[p] );
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3];
+}
+
+static void r300SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
+{
+ r300ContextPtr r300 = R300_CONTEXT(ctx);
+ GLuint p;
+
+ /* no VAP UCP on non-TCL chipsets */
+ if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
+ return;
+
+ p = cap - GL_CLIP_PLANE0;
+ R300_STATECHANGE(r300, vap_clip_cntl);
+ if (state) {
+ r300->hw.vap_clip_cntl.cmd[1] |= (R300_VAP_UCP_ENABLE_0 << p);
+ r300ClipPlane(ctx, cap, NULL);
+ } else {
+ r300->hw.vap_clip_cntl.cmd[1] &= ~(R300_VAP_UCP_ENABLE_0 << p);
+ }
+}
+
/**
* Update our tracked culling state based on Mesa's state.
*/
r300->hw.cul.cmd[R300_CUL_CULL] = val;
}
+static void r300SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
+{
+ r300ContextPtr r300 = R300_CONTEXT(ctx);
+
+ R300_STATECHANGE(r300, occlusion_cntl);
+ if (state) {
+ r300->hw.occlusion_cntl.cmd[1] |= (3 << 0);
+ } else {
+ r300->hw.occlusion_cntl.cmd[1] &= ~(3 << 0);
+ }
+}
+
static void r300SetEarlyZState(GLcontext * ctx)
{
/* updates register R300_RB3D_EARLY_Z (0x4F14)
R300_STATECHANGE(r300, zstencil_format);
switch (ctx->Visual.depthBits) {
case 16:
- r300->hw.zstencil_format.cmd[1] = R300_DEPTH_FORMAT_16BIT_INT_Z;
+ r300->hw.zstencil_format.cmd[1] = ZB_FORMAR_DEPTHFORMAT_16BIT_INT_Z;
break;
case 24:
- r300->hw.zstencil_format.cmd[1] = R300_DEPTH_FORMAT_24BIT_INT_Z;
+ r300->hw.zstencil_format.cmd[1] = ZB_FORMAR_DEPTHFORMAT_24BIT_INT_Z;
break;
default:
fprintf(stderr, "Error: Unsupported depth %d... exiting\n", ctx->Visual.depthBits);
_mesa_exit(-1);
}
- // r300->hw.zstencil_format.cmd[1] |= R300_DEPTH_FORMAT_UNK32;
-
if (ctx->Color.AlphaEnabled && ctx->Color.AlphaFunc != GL_ALWAYS)
/* disable early Z */
r300->hw.zstencil_format.cmd[2] = R300_EARLY_Z_DISABLE;
switch (ctx->Color.AlphaFunc) {
case GL_NEVER:
- pp_misc |= R300_ALPHA_TEST_FAIL;
+ pp_misc |= FG_ALPHA_FUNC_NEVER;
break;
case GL_LESS:
- pp_misc |= R300_ALPHA_TEST_LESS;
+ pp_misc |= FG_ALPHA_FUNC_LESS;
break;
case GL_EQUAL:
- pp_misc |= R300_ALPHA_TEST_EQUAL;
+ pp_misc |= FG_ALPHA_FUNC_EQUAL;
break;
case GL_LEQUAL:
- pp_misc |= R300_ALPHA_TEST_LEQUAL;
+ pp_misc |= FG_ALPHA_FUNC_LE;
break;
case GL_GREATER:
- pp_misc |= R300_ALPHA_TEST_GREATER;
+ pp_misc |= FG_ALPHA_FUNC_GREATER;
break;
case GL_NOTEQUAL:
- pp_misc |= R300_ALPHA_TEST_NEQUAL;
+ pp_misc |= FG_ALPHA_FUNC_NOTEQUAL;
break;
case GL_GEQUAL:
- pp_misc |= R300_ALPHA_TEST_GEQUAL;
+ pp_misc |= FG_ALPHA_FUNC_GE;
break;
case GL_ALWAYS:
- /*pp_misc |= R300_ALPHA_TEST_PASS; */
+ /*pp_misc |= FG_ALPHA_FUNC_ALWAYS; */
really_enabled = GL_FALSE;
break;
}
if (really_enabled) {
- pp_misc |= R300_ALPHA_TEST_ENABLE;
+ pp_misc |= FG_ALPHA_FUNC_ENABLE;
pp_misc |= (refByte & R300_REF_ALPHA_MASK);
} else {
pp_misc = 0x0;
r300SetEarlyZState(ctx);
}
+static void r300SetStencilState(GLcontext * ctx, GLboolean state)
+{
+ r300ContextPtr r300 = R300_CONTEXT(ctx);
+
+ if (r300->state.stencil.hw_stencil) {
+ R300_STATECHANGE(r300, zs);
+ if (state) {
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] |=
+ R300_RB3D_STENCIL_ENABLE;
+ } else {
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] &=
+ ~R300_RB3D_STENCIL_ENABLE;
+ }
+ } else {
+#if R200_MERGED
+ FALLBACK(&r300->radeon, RADEON_FALLBACK_STENCIL, state);
+#endif
+ }
+}
+
static void r300UpdatePolygonMode(GLcontext * ctx)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
- uint32_t hw_mode = 0;
+ uint32_t hw_mode = GA_POLY_MODE_DISABLE;
+ /* Only do something if a polygon mode is wanted, default is GL_FILL */
if (ctx->Polygon.FrontMode != GL_FILL ||
ctx->Polygon.BackMode != GL_FILL) {
GLenum f, b;
+ /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
+ * correctly by selecting the correct front and back face
+ */
if (ctx->Polygon.FrontFace == GL_CCW) {
f = ctx->Polygon.FrontMode;
b = ctx->Polygon.BackMode;
b = ctx->Polygon.FrontMode;
}
- hw_mode |= R300_PM_ENABLED;
+ /* Enable polygon mode */
+ hw_mode |= GA_POLY_MODE_DUAL;
switch (f) {
case GL_LINE:
- hw_mode |= R300_PM_FRONT_LINE;
+ hw_mode |= GA_POLY_MODE_FRONT_PTYPE_LINE;
break;
- case GL_POINT: /* noop */
- hw_mode |= R300_PM_FRONT_POINT;
+ case GL_POINT:
+ hw_mode |= GA_POLY_MODE_FRONT_PTYPE_POINT;
break;
case GL_FILL:
- hw_mode |= R300_PM_FRONT_FILL;
+ hw_mode |= GA_POLY_MODE_FRONT_PTYPE_TRI;
break;
}
switch (b) {
case GL_LINE:
- hw_mode |= R300_PM_BACK_LINE;
+ hw_mode |= GA_POLY_MODE_BACK_PTYPE_LINE;
break;
- case GL_POINT: /* noop */
- hw_mode |= R300_PM_BACK_POINT;
+ case GL_POINT:
+ hw_mode |= GA_POLY_MODE_BACK_PTYPE_POINT;
break;
case GL_FILL:
- hw_mode |= R300_PM_BACK_FILL;
+ hw_mode |= GA_POLY_MODE_BACK_PTYPE_TRI;
break;
}
}
GLboolean r, GLboolean g, GLboolean b, GLboolean a)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
- int mask = (r ? R300_COLORMASK0_R : 0) |
- (g ? R300_COLORMASK0_G : 0) |
- (b ? R300_COLORMASK0_B : 0) | (a ? R300_COLORMASK0_A : 0);
+ int mask = (r ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) |
+ (g ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) |
+ (b ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
+ (a ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0);
if (mask != r300->hw.cmk.cmd[R300_CMK_COLORMASK]) {
R300_STATECHANGE(r300, cmk);
R300_STATECHANGE(r300, fogs);
r300->hw.fogs.cmd[R300_FOGS_STATE] =
(r300->hw.fogs.
- cmd[R300_FOGS_STATE] & ~R300_FOG_MODE_MASK) |
- R300_FOG_MODE_LINEAR;
+ cmd[R300_FOGS_STATE] & ~FG_FOG_BLEND_FN_MASK) |
+ FG_FOG_BLEND_FN_LINEAR;
if (ctx->Fog.Start == ctx->Fog.End) {
fogScale.f = -1.0;
R300_STATECHANGE(r300, fogs);
r300->hw.fogs.cmd[R300_FOGS_STATE] =
(r300->hw.fogs.
- cmd[R300_FOGS_STATE] & ~R300_FOG_MODE_MASK) |
- R300_FOG_MODE_EXP;
+ cmd[R300_FOGS_STATE] & ~FG_FOG_BLEND_FN_MASK) |
+ FG_FOG_BLEND_FN_EXP;
fogScale.f = 0.0933 * ctx->Fog.Density;
fogStart.f = 0.0;
break;
R300_STATECHANGE(r300, fogs);
r300->hw.fogs.cmd[R300_FOGS_STATE] =
(r300->hw.fogs.
- cmd[R300_FOGS_STATE] & ~R300_FOG_MODE_MASK) |
- R300_FOG_MODE_EXP2;
+ cmd[R300_FOGS_STATE] & ~FG_FOG_BLEND_FN_MASK) |
+ FG_FOG_BLEND_FN_EXP2;
fogScale.f = 0.3 * ctx->Fog.Density;
fogStart.f = 0.0;
default:
}
}
+static void r300SetFogState(GLcontext * ctx, GLboolean state)
+{
+ r300ContextPtr r300 = R300_CONTEXT(ctx);
+
+ R300_STATECHANGE(r300, fogs);
+ if (state) {
+ r300->hw.fogs.cmd[R300_FOGS_STATE] |= FG_FOG_BLEND_ENABLE;
+
+ r300Fogfv(ctx, GL_FOG_MODE, NULL);
+ r300Fogfv(ctx, GL_FOG_DENSITY, &ctx->Fog.Density);
+ r300Fogfv(ctx, GL_FOG_START, &ctx->Fog.Start);
+ r300Fogfv(ctx, GL_FOG_END, &ctx->Fog.End);
+ r300Fogfv(ctx, GL_FOG_COLOR, ctx->Fog.Color);
+ } else {
+ r300->hw.fogs.cmd[R300_FOGS_STATE] &= ~FG_FOG_BLEND_ENABLE;
+ }
+}
+
/* =============================================================
* Point state
*/
static void r300PointSize(GLcontext * ctx, GLfloat size)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- size = ctx->Point._Size;
+ /* same size limits for AA, non-AA points */
+ size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
R300_STATECHANGE(r300, ps);
r300->hw.ps.cmd[R300_PS_POINTSIZE] =
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
- widthf = ctx->Line._Width;
-
+ widthf = CLAMP(widthf,
+ ctx->Const.MinPointSize,
+ ctx->Const.MaxPointSize);
R300_STATECHANGE(r300, lcntl);
r300->hw.lcntl.cmd[1] =
R300_LINE_CNT_HO | R300_LINE_CNT_VE | (int)(widthf * 6.0);
r300ContextPtr rmesa = R300_CONTEXT(ctx);
GLuint refmask =
(((ctx->Stencil.
- Ref[0] & 0xff) << R300_RB3D_ZS2_STENCIL_REF_SHIFT) | ((ctx->
+ Ref[0] & 0xff) << ZB_STENCILREFMASK_STENCILREF_SHIFT) | ((ctx->
Stencil.
ValueMask
[0] &
0xff)
<<
- R300_RB3D_ZS2_STENCIL_MASK_SHIFT));
+ ZB_STENCILREFMASK_STENCILMASK_SHIFT));
GLuint flag;
R300_RB3D_ZS1_BACK_FUNC_SHIFT));
rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
- ~((R300_RB3D_ZS2_STENCIL_MASK <<
- R300_RB3D_ZS2_STENCIL_REF_SHIFT) |
- (R300_RB3D_ZS2_STENCIL_MASK << R300_RB3D_ZS2_STENCIL_MASK_SHIFT));
+ ~((ZB_STENCILREFMASK_STENCIL_MASK << ZB_STENCILREFMASK_STENCILREF_SHIFT) |
+ (ZB_STENCILREFMASK_STENCIL_MASK << ZB_STENCILREFMASK_STENCILMASK_SHIFT));
flag = translate_func(ctx->Stencil.Function[0]);
rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
R300_STATECHANGE(rmesa, zs);
rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
- ~(R300_RB3D_ZS2_STENCIL_MASK <<
- R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT);
+ ~(ZB_STENCILREFMASK_STENCIL_MASK <<
+ ZB_STENCILREFMASK_STENCILWRITEMASK_SHIFT);
rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |=
(ctx->Stencil.
- WriteMask[0] & 0xff) << R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT;
+ WriteMask[0] & ZB_STENCILREFMASK_STENCIL_MASK) <<
+ ZB_STENCILREFMASK_STENCILWRITEMASK_SHIFT;
}
static void r300StencilOpSeparate(GLcontext * ctx, GLenum face,
r300ContextPtr rmesa = R300_CONTEXT(ctx);
rmesa->state.stencil.clear =
- ((GLuint) (ctx->Stencil.Clear & 0xff) |
- (R300_RB3D_ZS2_STENCIL_MASK <<
- R300_RB3D_ZS2_STENCIL_MASK_SHIFT) | ((ctx->Stencil.
- WriteMask[0] & 0xff) <<
- R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT));
+ ((GLuint) (ctx->Stencil.Clear & ZB_STENCILREFMASK_STENCIL_MASK) |
+ (ZB_STENCILREFMASK_STENCIL_MASK << ZB_STENCILREFMASK_STENCILMASK_SHIFT) |
+ ((ctx->Stencil.WriteMask[0] & ZB_STENCILREFMASK_STENCIL_MASK) <<
+ ZB_STENCILREFMASK_STENCILMASK_SHIFT));
}
/* =============================================================
struct gl_framebuffer *fb = ctx->DrawBuffer;
driRenderbuffer *drb;
- if (fb->_ColorDrawBufferMask[0] == BUFFER_BIT_FRONT_LEFT) {
+ if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
/* draw to front */
drb =
(driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT].
Renderbuffer;
- } else if (fb->_ColorDrawBufferMask[0] == BUFFER_BIT_BACK_LEFT) {
+ } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
/* draw to back */
drb =
(driRenderbuffer *) fb->Attachment[BUFFER_BACK_LEFT].
}
r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_FILTER_0, last_hw_tmu + 1);
+ cmdpacket0(R300_TX_FILTER0_0, last_hw_tmu + 1);
r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
cmdpacket0(R300_TX_FILTER1_0, last_hw_tmu + 1);
r300->hw.tex.size.cmd[R300_TEX_CMD_0] =
r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
cmdpacket0(R300_TX_FORMAT_0, last_hw_tmu + 1);
r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_PITCH_0, last_hw_tmu + 1);
+ cmdpacket0(R300_TX_FORMAT2_0, last_hw_tmu + 1);
r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
cmdpacket0(R300_TX_OFFSET_0, last_hw_tmu + 1);
r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
if (!fp) /* should only happenen once, just after context is created */
return;
- R300_STATECHANGE(r300, fpt);
-
- for (i = 0; i < fp->tex.length; i++) {
- int unit;
- int opcode;
- unsigned long val;
-
- unit = fp->tex.inst[i] >> R300_FPITX_IMAGE_SHIFT;
- unit &= 15;
-
- val = fp->tex.inst[i];
- val &= ~R300_FPITX_IMAGE_MASK;
- opcode =
- (val & R300_FPITX_OPCODE_MASK) >> R300_FPITX_OPCODE_SHIFT;
- if (opcode == R300_FPITX_OP_KIL) {
- r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
- } else {
- if (tmu_mappings[unit] >= 0) {
- val |=
- tmu_mappings[unit] <<
- R300_FPITX_IMAGE_SHIFT;
+ if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
+ R300_STATECHANGE(r300, fpt);
+
+ for (i = 0; i < fp->tex.length; i++) {
+ int unit;
+ int opcode;
+ unsigned long val;
+
+ unit = fp->tex.inst[i] >> R300_FPITX_IMAGE_SHIFT;
+ unit &= 15;
+
+ val = fp->tex.inst[i];
+ val &= ~R300_FPITX_IMAGE_MASK;
+
+ opcode =
+ (val & R300_FPITX_OPCODE_MASK) >> R300_FPITX_OPCODE_SHIFT;
+ if (opcode == R300_FPITX_OP_KIL) {
r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
} else {
- // We get here when the corresponding texture image is incomplete
- // (e.g. incomplete mipmaps etc.)
- r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
+ if (tmu_mappings[unit] >= 0) {
+ val |=
+ tmu_mappings[unit] <<
+ R300_FPITX_IMAGE_SHIFT;
+ r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
+ } else {
+ // We get here when the corresponding texture image is incomplete
+ // (e.g. incomplete mipmaps etc.)
+ r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
+ }
}
}
+
+ r300->hw.fpt.cmd[R300_FPT_CMD_0] =
+ cmdpacket0(R300_PFS_TEXI_0, fp->tex.length);
}
- r300->hw.fpt.cmd[R300_FPT_CMD_0] =
- cmdpacket0(R300_PFS_TEXI_0, fp->tex.length);
-
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "TX_ENABLE: %08x last_hw_tmu=%d\n",
r300->hw.txe.cmd[R300_TXE_ENABLE], last_hw_tmu);
/* I'm still unsure if these are needed */
GLuint interp_magic[8] = {
0x00,
- R300_RS_INTERP_1_UNKNOWN,
- R300_RS_INTERP_2_UNKNOWN,
- R300_RS_INTERP_3_UNKNOWN,
+ R300_RS_COL_PTR(1),
+ R300_RS_COL_PTR(2),
+ R300_RS_COL_PTR(3),
0x00,
0x00,
0x00,
fp_reg = in_texcoords = col_interp_nr = high_rr = 0;
- r300->hw.rr.cmd[R300_RR_ROUTE_1] = 0;
+ r300->hw.rr.cmd[R300_RR_INST_1] = 0;
if (InputsRead & FRAG_BIT_WPOS) {
for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
}
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
- r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 | R300_RS_INTERP_USED | (in_texcoords << R300_RS_INTERP_SRC_SHIFT)
+ r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | (in_texcoords << R300_RS_INTERP_SRC_SHIFT)
| interp_magic[i];
- r300->hw.rr.cmd[R300_RR_ROUTE_0 + fp_reg] = 0;
+ r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] = 0;
+ if (InputsRead & (FRAG_BIT_TEX0 << i)) {
+ //assert(r300->state.texture.tc_count != 0);
+ r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] |= R300_RS_INST_TEX_CN_WRITE | i /* source INTERP */
+ | (fp_reg << R300_RS_INST_TEX_ADDR_SHIFT);
+ high_rr = fp_reg;
+
+ /* Passing invalid data here can lock the GPU. */
+ if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
+ InputsRead &= ~(FRAG_BIT_TEX0 << i);
+ fp_reg++;
+ } else {
+ WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
+ }
+ }
+ /* Need to count all coords enabled at vof */
+ if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
+ in_texcoords++;
+ }
+ }
+
+ if (InputsRead & FRAG_BIT_COL0) {
+ if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
+ r300->hw.rr.cmd[R300_RR_INST_0] |= R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_CN_WRITE | (fp_reg++ << R300_RS_INST_COL_ADDR_SHIFT);
+ InputsRead &= ~FRAG_BIT_COL0;
+ col_interp_nr++;
+ } else {
+ WARN_ONCE("fragprog wants col0, vp doesn't provide it\n");
+ }
+ }
+
+ if (InputsRead & FRAG_BIT_COL1) {
+ if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
+ r300->hw.rr.cmd[R300_RR_INST_1] |= R300_RS_INST_COL_ID(1) | R300_RS_INST_COL_CN_WRITE | (fp_reg++ << R300_RS_INST_COL_ADDR_SHIFT);
+ InputsRead &= ~FRAG_BIT_COL1;
+ if (high_rr < 1)
+ high_rr = 1;
+ col_interp_nr++;
+ } else {
+ WARN_ONCE("fragprog wants col1, vp doesn't provide it\n");
+ }
+ }
+
+ /* Need at least one. This might still lock as the values are undefined... */
+ if (in_texcoords == 0 && col_interp_nr == 0) {
+ r300->hw.rr.cmd[R300_RR_INST_0] |= R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_CN_WRITE | (fp_reg++ << R300_RS_INST_COL_ADDR_SHIFT);
+ col_interp_nr++;
+ }
+
+ r300->hw.rc.cmd[1] = 0 | ((in_texcoords << 2) << R300_IT_COUNT_SHIFT)
+ | (col_interp_nr << R300_IC_COUNT_SHIFT)
+ | R300_HIRES_EN;
+
+ assert(high_rr >= 0);
+ r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, high_rr + 1);
+ r300->hw.rc.cmd[2] = 0xC0 | high_rr;
+
+ if (InputsRead)
+ WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
+}
+
+static void r500SetupRSUnit(GLcontext * ctx)
+{
+ r300ContextPtr r300 = R300_CONTEXT(ctx);
+ /* I'm still unsure if these are needed */
+ GLuint interp_magic[8] = {
+ 0x00,
+ 1 << 24,
+ 2 << 24,
+ 3 << 24,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00
+ };
+ union r300_outputs_written OutputsWritten;
+ GLuint InputsRead;
+ int fp_reg, high_rr;
+ int in_texcoords, col_interp_nr;
+ int i;
+
+ if (hw_tcl_on)
+ OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
+ else
+ RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset);
+
+ if (ctx->FragmentProgram._Current)
+ InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
+ else {
+ fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
+ return; /* This should only ever happen once.. */
+ }
+
+ R300_STATECHANGE(r300, ri);
+ R300_STATECHANGE(r300, rc);
+ R300_STATECHANGE(r300, rr);
+
+ fp_reg = in_texcoords = col_interp_nr = high_rr = 0;
+
+ r300->hw.rr.cmd[R300_RR_INST_1] = 0;
+
+ if (InputsRead & FRAG_BIT_WPOS) {
+ for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
+ if (!(InputsRead & (FRAG_BIT_TEX0 << i)))
+ break;
+
+ if (i == ctx->Const.MaxTextureUnits) {
+ fprintf(stderr, "\tno free texcoord found...\n");
+ _mesa_exit(-1);
+ }
+
+ InputsRead |= (FRAG_BIT_TEX0 << i);
+ InputsRead &= ~FRAG_BIT_WPOS;
+ }
+
+ for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
+
+ // r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | (in_texcoords << R300_RS_INTERP_SRC_SHIFT)
+
+ r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = (0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (2 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+ (3 << R500_RS_IP_TEX_PTR_Q_SHIFT) |
+ (in_texcoords << 0) | interp_magic[i];
+
+ r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] = 0;
if (InputsRead & (FRAG_BIT_TEX0 << i)) {
//assert(r300->state.texture.tc_count != 0);
- r300->hw.rr.cmd[R300_RR_ROUTE_0 + fp_reg] |= R300_RS_ROUTE_ENABLE | i /* source INTERP */
- | (fp_reg << R300_RS_ROUTE_DEST_SHIFT);
+ r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] |= R500_RS_INST_TEX_CN_WRITE | i /* source INTERP */
+ | (fp_reg << R500_RS_INST_TEX_ADDR_SHIFT);
high_rr = fp_reg;
/* Passing invalid data here can lock the GPU. */
if (InputsRead & FRAG_BIT_COL0) {
if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
- r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT);
+ // r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT);
+ r300->hw.rr.cmd[R300_RR_INST_0] |= 0 | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_ADDR_SHIFT);
InputsRead &= ~FRAG_BIT_COL0;
col_interp_nr++;
} else {
if (InputsRead & FRAG_BIT_COL1) {
if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
- r300->hw.rr.cmd[R300_RR_ROUTE_1] |= R300_RS_ROUTE_1_UNKNOWN11 | R300_RS_ROUTE_1_COLOR1 | (fp_reg++ << R300_RS_ROUTE_1_COLOR1_DEST_SHIFT);
+ // r300->hw.rr.cmd[R300_RR_ROUTE_1] |= R300_RS_ROUTE_1_UNKNOWN11 | R300_RS_ROUTE_1_COLOR1 | (fp_reg++ << R300_RS_ROUTE_1_COLOR1_DEST_SHIFT);
+ r300->hw.rr.cmd[R300_RR_INST_1] |= (1 << 12) | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_ADDR_SHIFT);
InputsRead &= ~FRAG_BIT_COL1;
if (high_rr < 1)
high_rr = 1;
/* Need at least one. This might still lock as the values are undefined... */
if (in_texcoords == 0 && col_interp_nr == 0) {
- r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT);
+ r300->hw.rr.cmd[R300_RR_INST_0] |= 0 | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_ADDR_SHIFT);
col_interp_nr++;
}
- r300->hw.rc.cmd[1] = 0 | (in_texcoords << R300_RS_CNTL_TC_CNT_SHIFT)
- | (col_interp_nr << R300_RS_CNTL_CI_CNT_SHIFT)
- | R300_RS_CNTL_0_UNKNOWN_18;
+ r300->hw.rc.cmd[1] = 0 | ((in_texcoords << 2) << R300_IT_COUNT_SHIFT)
+ | (col_interp_nr << R300_IC_COUNT_SHIFT)
+ | R300_HIRES_EN;
assert(high_rr >= 0);
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_ROUTE_0, high_rr + 1);
+ r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, high_rr + 1);
r300->hw.rc.cmd[2] = 0xC0 | high_rr;
if (InputsRead)
WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
}
+
+
+
#define bump_vpu_count(ptr, new_count) do{\
drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
int _nc=(new_count)/4; \
for (i = VERT_ATTRIB_POS; i < VERT_ATTRIB_MAX; i++) {
if (rmesa->state.sw_tcl_inputs[i] != -1) {
- prog->program.body.i[program_end].op = EASY_VSF_OP(MUL, o_reg++, ALL, RESULT);
- prog->program.body.i[program_end].src[0] = VSF_REG(rmesa->state.sw_tcl_inputs[i]);
- prog->program.body.i[program_end].src[1] = VSF_ATTR_UNITY(rmesa->state.sw_tcl_inputs[i]);
- prog->program.body.i[program_end].src[2] = VSF_UNITY(rmesa->state.sw_tcl_inputs[i]);
- program_end++;
+ prog->program.body.i[program_end + 0] = PVS_OP_DST_OPERAND(VE_MULTIPLY, GL_FALSE, GL_FALSE, o_reg++, VSF_FLAG_ALL, PVS_DST_REG_OUT);
+ prog->program.body.i[program_end + 1] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
+ prog->program.body.i[program_end + 2] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
+ prog->program.body.i[program_end + 3] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
+ program_end += 4;
}
}
- prog->program.length = program_end * 4;
+ prog->program.length = program_end;
- r300SetupVertexProgramFragment(rmesa, VSF_DEST_PROGRAM, &(prog->program));
+ r300SetupVertexProgramFragment(rmesa, R300_PVS_UPLOAD_PROGRAM,
+ &(prog->program));
inst_count = (prog->program.length / 4) - 1;
R300_STATECHANGE(rmesa, pvs);
rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] =
- (0 << R300_PVS_CNTL_1_PROGRAM_START_SHIFT) |
- (inst_count << R300_PVS_CNTL_1_POS_END_SHIFT) |
- (inst_count << R300_PVS_CNTL_1_PROGRAM_END_SHIFT);
+ (0 << R300_PVS_CNTL_1_PROGRAM_START_SHIFT) |
+ (inst_count << R300_PVS_CNTL_1_POS_END_SHIFT) |
+ (inst_count << R300_PVS_CNTL_1_PROGRAM_END_SHIFT);
rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] =
- (0 << R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT) |
- (param_count << R300_PVS_CNTL_2_PARAM_COUNT_SHIFT);
+ (0 << R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT) |
+ (param_count << R300_PVS_CNTL_2_PARAM_COUNT_SHIFT);
rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] =
- (inst_count << R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT) |
- (inst_count << R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT);
+ (inst_count << R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT) |
+ (inst_count << R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT);
}
static void r300SetupRealVertexProgram(r300ContextPtr rmesa)
bump_vpu_count(rmesa->hw.vpp.cmd, param_count);
param_count /= 4;
- r300SetupVertexProgramFragment(rmesa, VSF_DEST_PROGRAM, &(prog->program));
+ r300SetupVertexProgramFragment(rmesa, R300_PVS_UPLOAD_PROGRAM, &(prog->program));
inst_count = (prog->program.length / 4) - 1;
R300_STATECHANGE(rmesa, pvs);
*/
static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__,
_mesa_lookup_enum_by_nr(cap),
state ? "GL_TRUE" : "GL_FALSE");
switch (cap) {
- /* Fast track this one...
- */
case GL_TEXTURE_1D:
case GL_TEXTURE_2D:
case GL_TEXTURE_3D:
+ /* empty */
break;
-
case GL_FOG:
- R300_STATECHANGE(r300, fogs);
- if (state) {
- r300->hw.fogs.cmd[R300_FOGS_STATE] |= R300_FOG_ENABLE;
-
- r300Fogfv(ctx, GL_FOG_MODE, NULL);
- r300Fogfv(ctx, GL_FOG_DENSITY, &ctx->Fog.Density);
- r300Fogfv(ctx, GL_FOG_START, &ctx->Fog.Start);
- r300Fogfv(ctx, GL_FOG_END, &ctx->Fog.End);
- r300Fogfv(ctx, GL_FOG_COLOR, ctx->Fog.Color);
- } else {
- r300->hw.fogs.cmd[R300_FOGS_STATE] &= ~R300_FOG_ENABLE;
- }
-
+ r300SetFogState(ctx, state);
break;
-
case GL_ALPHA_TEST:
r300SetAlphaState(ctx);
break;
-
case GL_BLEND:
case GL_COLOR_LOGIC_OP:
r300SetBlendState(ctx);
break;
-
+ case GL_CLIP_PLANE0:
+ case GL_CLIP_PLANE1:
+ case GL_CLIP_PLANE2:
+ case GL_CLIP_PLANE3:
+ case GL_CLIP_PLANE4:
+ case GL_CLIP_PLANE5:
+ r300SetClipPlaneState(ctx, cap, state);
+ break;
case GL_DEPTH_TEST:
r300SetDepthState(ctx);
break;
-
case GL_STENCIL_TEST:
- if (r300->state.stencil.hw_stencil) {
- R300_STATECHANGE(r300, zs);
- if (state) {
- r300->hw.zs.cmd[R300_ZS_CNTL_0] |=
- R300_RB3D_STENCIL_ENABLE;
- } else {
- r300->hw.zs.cmd[R300_ZS_CNTL_0] &=
- ~R300_RB3D_STENCIL_ENABLE;
- }
- } else {
-#if R200_MERGED
- FALLBACK(&r300->radeon, RADEON_FALLBACK_STENCIL, state);
-#endif
- }
+ r300SetStencilState(ctx, state);
break;
-
case GL_CULL_FACE:
r300UpdateCulling(ctx);
break;
-
case GL_POLYGON_OFFSET_POINT:
case GL_POLYGON_OFFSET_LINE:
case GL_POLYGON_OFFSET_FILL:
- R300_STATECHANGE(r300, occlusion_cntl);
- if (state) {
- r300->hw.occlusion_cntl.cmd[1] |= (3 << 0);
- } else {
- r300->hw.occlusion_cntl.cmd[1] &= ~(3 << 0);
- }
+ r300SetPolygonOffsetState(ctx, state);
break;
default:
radeonEnable(ctx, cap, state);
- return;
+ break;
}
}
r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
- if (!has_tcl)
- r300->hw.vap_cntl.cmd[1] = 0x0014045a;
+ /* setup the VAP */
+ /* for tcl, PVS_NUM_SLOTS, PVS_NUM_CNTLRS, VF_MAX_VTX_NUM need to be adjusted
+ * dynamically. PVS_NUM_FPUS is fixed based on asic
+ */
+ if (has_tcl) {
+ r300->hw.vap_cntl.cmd[1] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (12 << R300_VF_MAX_VTX_NUM_SHIFT));
+ if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
+ r300->hw.vap_cntl.cmd[1] |= R500_TCL_STATE_OPTIMIZATION;
+ } else
+ r300->hw.vap_cntl.cmd[1] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (5 << R300_VF_MAX_VTX_NUM_SHIFT));
+
+ if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
+ r300->hw.vap_cntl.cmd[1] |= (2 << R300_PVS_NUM_FPUS_SHIFT);
+ else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
+ (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560))
+ r300->hw.vap_cntl.cmd[1] |= (5 << R300_PVS_NUM_FPUS_SHIFT);
+ else if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)
+ r300->hw.vap_cntl.cmd[1] |= (6 << R300_PVS_NUM_FPUS_SHIFT);
+ else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
+ (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580) ||
+ (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
+ r300->hw.vap_cntl.cmd[1] |= (8 << R300_PVS_NUM_FPUS_SHIFT);
else
- r300->hw.vap_cntl.cmd[1] = 0x0030045A; //0x0030065a /* Dangerous */
+ r300->hw.vap_cntl.cmd[1] |= (4 << R300_PVS_NUM_FPUS_SHIFT);
r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA
| R300_VPORT_X_OFFSET_ENA
| R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT;
r300->hw.vte.cmd[2] = 0x00000008;
- r300->hw.unk2134.cmd[1] = 0x00FFFFFF;
- r300->hw.unk2134.cmd[2] = 0x00000000;
+ r300->hw.vap_vf_max_vtx_indx.cmd[1] = 0x00FFFFFF;
+ r300->hw.vap_vf_max_vtx_indx.cmd[2] = 0x00000000;
#ifdef MESA_LITTLE_ENDIAN
r300->hw.vap_cntl_status.cmd[1] = R300_VC_NO_SWAP;
if (!has_tcl)
r300->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS;
- r300->hw.unk21DC.cmd[1] = 0xAAAAAAAA;
-
- r300->hw.unk221C.cmd[1] = R300_221C_NORMAL;
-
- r300->hw.vap_clip.cmd[1] = r300PackFloat32(1.0); /* X */
- r300->hw.vap_clip.cmd[2] = r300PackFloat32(1.0); /* X */
- r300->hw.vap_clip.cmd[3] = r300PackFloat32(1.0); /* Y */
- r300->hw.vap_clip.cmd[4] = r300PackFloat32(1.0); /* Y */
+ r300->hw.vap_psc_sgn_norm_cntl.cmd[1] = 0xAAAAAAAA;
/* XXX: Other families? */
if (has_tcl) {
+ r300->hw.vap_clip_cntl.cmd[1] = R300_PS_UCP_MODE_DIST_COP;
+
+ r300->hw.vap_clip.cmd[1] = r300PackFloat32(1.0); /* X */
+ r300->hw.vap_clip.cmd[2] = r300PackFloat32(1.0); /* X */
+ r300->hw.vap_clip.cmd[3] = r300PackFloat32(1.0); /* Y */
+ r300->hw.vap_clip.cmd[4] = r300PackFloat32(1.0); /* Y */
+
switch (r300->radeon.radeonScreen->chip_family) {
case CHIP_FAMILY_R300:
- r300->hw.unk2288.cmd[1] = R300_2288_R300;
+ r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_R300;
break;
default:
- r300->hw.unk2288.cmd[1] = R300_2288_RV350;
+ r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_RV350;
break;
}
}
r300->hw.gb_enable.cmd[1] = R300_GB_POINT_STUFF_ENABLE
| R300_GB_LINE_STUFF_ENABLE
- | R300_GB_TRIANGLE_STUFF_ENABLE /*| R300_GB_UNK31 */ ;
+ | R300_GB_TRIANGLE_STUFF_ENABLE;
r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666;
r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666;
- /* XXX: Other families? */
+ /* num pipes needs to be read back from the GB_PIPE_SELECT register
+ * on r4xx/r5xx/rs4xx/rs6xx
+ * should move this to the drm
+ */
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] =
- R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16;
+ R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16 /*| R300_GB_SUBPIXEL_1_16*/;
switch (r300->radeon.radeonScreen->chip_family) {
case CHIP_FAMILY_R300:
case CHIP_FAMILY_R350:
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
R300_GB_TILE_PIPE_COUNT_R300;
break;
+ case CHIP_FAMILY_RV350:
+ case CHIP_FAMILY_RV515:
+ case CHIP_FAMILY_RV530:
case CHIP_FAMILY_RV410:
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_RV410;
+ R300_GB_TILE_PIPE_COUNT_RV300;
break;
case CHIP_FAMILY_R420:
+ case CHIP_FAMILY_R520:
+ case CHIP_FAMILY_R580:
+ case CHIP_FAMILY_RV560:
+ case CHIP_FAMILY_RV570:
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
R300_GB_TILE_PIPE_COUNT_R420;
break;
default:
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_RV300;
+ R300_GB_TILE_DISABLE; /* TODO: This disables tiling totally. I guess it happened accidentially. */
break;
}
r300->hw.gb_misc.cmd[R300_GB_MISC_SELECT] = R300_GB_FOG_SELECT_1_1_W;
/* XXX: Enable anti-aliasing? */
- r300->hw.gb_misc.cmd[R300_GB_MISC_AA_CONFIG] = R300_AA_DISABLE;
+ r300->hw.gb_misc.cmd[R300_GB_MISC_AA_CONFIG] = GB_AA_CONFIG_AA_DISABLE;
- r300->hw.unk4200.cmd[1] = r300PackFloat32(0.0);
- r300->hw.unk4200.cmd[2] = r300PackFloat32(0.0);
- r300->hw.unk4200.cmd[3] = r300PackFloat32(1.0);
- r300->hw.unk4200.cmd[4] = r300PackFloat32(1.0);
+ r300->hw.ga_point_s0.cmd[1] = r300PackFloat32(0.0);
+ r300->hw.ga_point_s0.cmd[2] = r300PackFloat32(0.0);
+ r300->hw.ga_point_s0.cmd[3] = r300PackFloat32(1.0);
+ r300->hw.ga_point_s0.cmd[4] = r300PackFloat32(1.0);
- r300->hw.unk4214.cmd[1] = 0x00050005;
+ r300->hw.ga_triangle_stipple.cmd[1] = 0x00050005;
r300PointSize(ctx, 1.0);
- r300->hw.unk4230.cmd[1] = 0x18000006;
- r300->hw.unk4230.cmd[2] = 0x00020006;
- r300->hw.unk4230.cmd[3] = r300PackFloat32(1.0 / 192.0);
+ r300->hw.ga_point_minmax.cmd[1] = 0x18000006;
+ r300->hw.ga_point_minmax.cmd[2] = 0x00020006;
+ r300->hw.ga_point_minmax.cmd[3] = r300PackFloat32(1.0 / 192.0);
r300LineWidth(ctx, 1.0);
- r300->hw.unk4260.cmd[1] = 0;
- r300->hw.unk4260.cmd[2] = r300PackFloat32(0.0);
- r300->hw.unk4260.cmd[3] = r300PackFloat32(1.0);
+ r300->hw.ga_line_stipple.cmd[1] = 0;
+ r300->hw.ga_line_stipple.cmd[2] = r300PackFloat32(0.0);
+ r300->hw.ga_line_stipple.cmd[3] = r300PackFloat32(1.0);
r300ShadeModel(ctx, ctx->Light.ShadeModel);
r300Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
r300Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
- r300->hw.unk42C0.cmd[1] = 0x4B7FFFFF;
- r300->hw.unk42C0.cmd[2] = 0x00000000;
+ r300->hw.su_depth_scale.cmd[1] = 0x4B7FFFFF;
+ r300->hw.su_depth_scale.cmd[2] = 0x00000000;
- r300->hw.unk43A4.cmd[1] = 0x0000001C;
- r300->hw.unk43A4.cmd[2] = 0x2DA49525;
+ r300->hw.sc_hyperz.cmd[1] = 0x0000001C;
+ r300->hw.sc_hyperz.cmd[2] = 0x2DA49525;
- r300->hw.unk43E8.cmd[1] = 0x00FFFFFF;
+ r300->hw.sc_screendoor.cmd[1] = 0x00FFFFFF;
- r300->hw.unk46A4.cmd[1] = 0x00001B01;
- r300->hw.unk46A4.cmd[2] = 0x00001B0F;
- r300->hw.unk46A4.cmd[3] = 0x00001B0F;
- r300->hw.unk46A4.cmd[4] = 0x00001B0F;
- r300->hw.unk46A4.cmd[5] = 0x00000001;
+ r300->hw.us_out_fmt.cmd[1] = 0x00001B01;
+ r300->hw.us_out_fmt.cmd[2] = 0x00001B0F;
+ r300->hw.us_out_fmt.cmd[3] = 0x00001B0F;
+ r300->hw.us_out_fmt.cmd[4] = 0x00001B0F;
+ r300->hw.us_out_fmt.cmd[5] = 0x00000001;
r300Enable(ctx, GL_FOG, ctx->Fog.Enabled);
r300Fogfv(ctx, GL_FOG_MODE, NULL);
r300Fogfv(ctx, GL_FOG_COLOR, ctx->Fog.Color);
r300Fogfv(ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL);
- r300->hw.unk4BD8.cmd[1] = 0;
+ r300->hw.fg_depth_src.cmd[1] = 0;
- r300->hw.unk4E00.cmd[1] = 0;
+ r300->hw.rb3d_cctl.cmd[1] = 0;
r300BlendColor(ctx, ctx->Color.BlendColor);
if (r300->radeon.sarea->tiling_enabled)
r300->hw.cb.cmd[R300_CB_PITCH] |= R300_COLOR_TILE_ENABLE;
- r300->hw.unk4E50.cmd[1] = 0;
- r300->hw.unk4E50.cmd[2] = 0;
- r300->hw.unk4E50.cmd[3] = 0;
- r300->hw.unk4E50.cmd[4] = 0;
- r300->hw.unk4E50.cmd[5] = 0;
- r300->hw.unk4E50.cmd[6] = 0;
- r300->hw.unk4E50.cmd[7] = 0;
- r300->hw.unk4E50.cmd[8] = 0;
- r300->hw.unk4E50.cmd[9] = 0;
+ r300->hw.rb3d_dither_ctl.cmd[1] = 0;
+ r300->hw.rb3d_dither_ctl.cmd[2] = 0;
+ r300->hw.rb3d_dither_ctl.cmd[3] = 0;
+ r300->hw.rb3d_dither_ctl.cmd[4] = 0;
+ r300->hw.rb3d_dither_ctl.cmd[5] = 0;
+ r300->hw.rb3d_dither_ctl.cmd[6] = 0;
+ r300->hw.rb3d_dither_ctl.cmd[7] = 0;
+ r300->hw.rb3d_dither_ctl.cmd[8] = 0;
+ r300->hw.rb3d_dither_ctl.cmd[9] = 0;
- r300->hw.unk4E88.cmd[1] = 0;
+ r300->hw.rb3d_aaresolve_ctl.cmd[1] = 0;
- r300->hw.unk4EA0.cmd[1] = 0x00000000;
- r300->hw.unk4EA0.cmd[2] = 0xffffffff;
+ r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000;
+ r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff;
r300->hw.zb.cmd[R300_ZB_OFFSET] =
r300->radeon.radeonScreen->depthOffset +
if (r300->radeon.sarea->tiling_enabled) {
/* XXX: Turn off when clearing buffers ? */
- r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTH_TILE_ENABLE;
+ r300->hw.zb.cmd[R300_ZB_PITCH] |= ZB_DEPTHPITCH_DEPTHMACROTILE_ENABLE;
if (ctx->Visual.depthBits == 24)
r300->hw.zb.cmd[R300_ZB_PITCH] |=
- R300_DEPTH_MICROTILE_ENABLE;
+ ZB_DEPTHPITCH_DEPTHMICROTILE_TILED;
}
- r300->hw.unk4F28.cmd[1] = 0;
+ r300->hw.zb_depthclearvalue.cmd[1] = 0;
r300->hw.unk4F30.cmd[1] = 0;
r300->hw.unk4F30.cmd[2] = 0;
- r300->hw.unk4F44.cmd[1] = 0;
+ r300->hw.zb_hiz_offset.cmd[1] = 0;
- r300->hw.unk4F54.cmd[1] = 0;
+ r300->hw.zb_hiz_pitch.cmd[1] = 0;
if (has_tcl) {
r300->hw.vps.cmd[R300_VPS_ZERO_0] = 0;
}
}
+#define bump_r500fp_count(ptr, new_count) do{\
+ drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
+ int _nc=(new_count)/6; \
+ assert(_nc < 256); \
+ if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
+} while(0)
+
+#define bump_r500fp_const_count(ptr, new_count) do{\
+ drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
+ int _nc=(new_count)/4; \
+ assert(_nc < 256); \
+ if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
+} while(0)
+
+static void r500SetupPixelShader(r300ContextPtr rmesa)
+{
+ GLcontext *ctx = rmesa->radeon.glCtx;
+ struct r300_fragment_program *fp = (struct r300_fragment_program *)
+ (char *)ctx->FragmentProgram._Current;
+ int i, k;
+
+ if (!fp) /* should only happenen once, just after context is created */
+ return;
+
+ /* emit the standard zero shader */
+ R300_STATECHANGE(rmesa, r500fp);
+ i = 1;
+ rmesa->hw.r500fp.cmd[i++] = R500_INST_TYPE_OUT |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_LAST |
+ R500_INST_RGB_OMASK_R |
+ R500_INST_RGB_OMASK_G |
+ R500_INST_RGB_OMASK_B |
+ R500_INST_ALPHA_OMASK;
+
+ rmesa->hw.r500fp.cmd[i++] = R500_RGB_ADDR0(0) |
+ R500_RGB_ADDR1(0) |
+ R500_RGB_ADDR1_CONST |
+ R500_RGB_ADDR2(0) |
+ R500_RGB_ADDR2_CONST |
+ R500_RGB_SRCP_OP_1_MINUS_2RGB0;
+ rmesa->hw.r500fp.cmd[i++] = R500_ALPHA_ADDR0(0) |
+ R500_ALPHA_ADDR1(0) |
+ R500_ALPHA_ADDR1_CONST |
+ R500_ALPHA_ADDR2(0) |
+ R500_ALPHA_ADDR2_CONST |
+ R500_ALPHA_SRCP_OP_1_MINUS_2A0;
+ rmesa->hw.r500fp.cmd[i++] = R500_ALU_RGB_SEL_A_SRC0 |
+ R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B |
+ R500_ALU_RGB_SEL_B_SRC0 |
+ R500_ALU_RGB_R_SWIZ_B_1 |
+ R500_ALU_RGB_B_SWIZ_B_1 |
+ R500_ALU_RGB_G_SWIZ_B_1;
+ rmesa->hw.r500fp.cmd[i++] = R500_ALPHA_OP_MAD |
+ R500_ALPHA_SWIZ_A_A |
+ R500_ALPHA_SWIZ_B_1;
+ rmesa->hw.r500fp.cmd[i++] = R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 |
+ R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0;
+
+ bump_r500fp_count(rmesa->hw.r500fp.cmd, 6);
+
+ R300_STATECHANGE(rmesa, r500fp_const);
+ for (i = 0; i < fp->const_nr; i++) {
+ rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(fp->constant[i][0]);
+ rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat24(fp->constant[i][1]);
+ rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(fp->constant[i][2]);
+ rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(fp->constant[i][3]);
+ }
+ bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, fp->const_nr * 4);
+
+}
+
void r300UpdateShaderStates(r300ContextPtr rmesa)
{
GLcontext *ctx;
r300UpdateTextureState(ctx);
- r300SetupPixelShader(rmesa);
+ if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
+ r500SetupPixelShader(rmesa);
+ else
+ r300SetupPixelShader(rmesa);
r300SetupTextures(ctx);
if ((rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
r300SetupVertexProgram(rmesa);
- r300SetupRSUnit(ctx);
+
+ if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
+ r500SetupRSUnit(ctx);
+ else
+ r300SetupRSUnit(ctx);
}
/**
switch (ctx->Visual.depthBits) {
case 16:
r300->state.depth.scale = 1.0 / (GLfloat) 0xffff;
- depth_fmt = R300_DEPTH_FORMAT_16BIT_INT_Z;
+ depth_fmt = ZB_FORMAR_DEPTHFORMAT_16BIT_INT_Z;
r300->state.stencil.clear = 0x00000000;
break;
case 24:
r300->state.depth.scale = 1.0 / (GLfloat) 0xffffff;
- depth_fmt = R300_DEPTH_FORMAT_24BIT_INT_Z;
+ depth_fmt = ZB_FORMAR_DEPTHFORMAT_24BIT_INT_Z;
r300->state.stencil.clear = 0x00ff0000;
break;
default:
(void)mode;
}
+void r300UpdateClipPlanes( GLcontext *ctx )
+{
+ r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ GLuint p;
+
+ for (p = 0; p < ctx->Const.MaxClipPlanes; p++) {
+ if (ctx->Transform.ClipPlanesEnabled & (1 << p)) {
+ GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
+
+ R300_STATECHANGE( rmesa, vpucp[p] );
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2];
+ rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3];
+ }
+ }
+}
+
/**
* Initialize driver's state callback functions
*/
functions->PolygonMode = r300PolygonMode;
functions->RenderMode = r300RenderMode;
+
+ functions->ClipPlane = r300ClipPlane;
}
projects / mesa.git / blobdiff