radeon: Add r6xx/r7xx chip family to get_chip_family_name

[mesa.git] / src / mesa / drivers / dri / r300 / r500_fragprog.h

diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.h b/src/mesa/drivers/dri/r300/r500_fragprog.h
index 72fca778455b13400f493838edd032bfd9721397..1179bf660738443f2e8f076eda9cba6acc6009e2 100644 (file)
--- a/src/mesa/drivers/dri/r300/r500_fragprog.h
+++ b/src/mesa/drivers/dri/r300/r500_fragprog.h
@@ -30,75 +30,23 @@
  *   Ben Skeggs <darktama@iinet.net.au>
  *   Jerome Glisse <j.glisse@gmail.com>
  */
-#ifndef __R300_FRAGPROG_H_
-#define __R300_FRAGPROG_H_
+#ifndef __R500_FRAGPROG_H_
+#define __R500_FRAGPROG_H_
 
-#include "glheader.h"
-#include "macros.h"
-#include "enums.h"
-#include "shader/program.h"
+#include "shader/prog_parameter.h"
 #include "shader/prog_instruction.h"
 
 #include "r300_context.h"
+#include "radeon_nqssadce.h"
 
-typedef struct r300_fragment_program_swizzle {
-       GLuint length;
-       GLuint src[4];
-       GLuint inst[8];
-} r300_fragment_program_swizzle_t;
+extern GLboolean r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler);
 
-/* supported hw opcodes */
-#define PFS_OP_MAD 0
-#define PFS_OP_DP3 1
-#define PFS_OP_DP4 2
-#define PFS_OP_MIN 3
-#define PFS_OP_MAX 4
-#define PFS_OP_CMP 5
-#define PFS_OP_FRC 6
-#define PFS_OP_EX2 7
-#define PFS_OP_LG2 8
-#define PFS_OP_RCP 9
-#define PFS_OP_RSQ 10
-#define PFS_OP_REPL_ALPHA 11
-#define PFS_OP_CMPH 12
-#define MAX_PFS_OP 12
+extern void r500FragmentProgramDump(union rX00_fragment_program_code *c);
 
-#define PFS_FLAG_SAT   (1 << 0)
-#define PFS_FLAG_ABS   (1 << 1)
+extern GLboolean r500FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg);
 
-#define ARG_NEG                        (1 << 5)
-#define ARG_ABS                        (1 << 6)
-#define ARG_MASK               (127 << 0)
-#define ARG_STRIDE             7
-#define SRC_CONST              (1 << 5)
-#define SRC_MASK               (63 << 0)
-#define SRC_STRIDE             6
+extern void r500FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src);
 
-#define NOP_INST0 (                                             \
-               (R300_FPI0_OUTC_MAD) |                           \
-               (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG0C_SHIFT) | \
-               (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG1C_SHIFT) | \
-               (R300_FPI0_ARGC_ZERO << R300_FPI0_ARG2C_SHIFT))
-#define NOP_INST1 (                                         \
-               ((0 | SRC_CONST) << R300_FPI1_SRC0C_SHIFT) | \
-               ((0 | SRC_CONST) << R300_FPI1_SRC1C_SHIFT) | \
-               ((0 | SRC_CONST) << R300_FPI1_SRC2C_SHIFT))
-#define NOP_INST2 ( \
-               (R300_FPI2_OUTA_MAD) |                           \
-               (R300_FPI2_ARGA_ZERO << R300_FPI2_ARG0A_SHIFT) | \
-               (R300_FPI2_ARGA_ZERO << R300_FPI2_ARG1A_SHIFT) | \
-               (R300_FPI2_ARGA_ZERO << R300_FPI2_ARG2A_SHIFT))
-#define NOP_INST3 (                                         \
-               ((0 | SRC_CONST) << R300_FPI3_SRC0A_SHIFT) | \
-               ((0 | SRC_CONST) << R300_FPI3_SRC1A_SHIFT) | \
-               ((0 | SRC_CONST) << R300_FPI3_SRC2A_SHIFT))
-
-#define DRI_CONF_FP_OPTIMIZATION_SPEED   0
-#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
-
-struct r300_fragment_program;
-
-extern void r300TranslateFragmentShader(r300ContextPtr r300,
-                                       struct r300_fragment_program *fp);
+extern GLboolean r500_transform_TEX(struct radeon_transform_context *t, struct prog_instruction* orig_inst, void* data);
 
 #endif