insert_at_tail(&context->radeon.hw.atomlist, &context->evergreen_atoms.ATOM); \
} while (0)
-static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_queryobj(struct gl_context *ctx, struct radeon_state_atom *atom)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct radeon_query_object *query = radeon->query.current;
return count;
}
-static void evergreenSendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendQueryBegin(struct gl_context *ctx, struct radeon_state_atom *atom)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct radeon_query_object *query = radeon->query.current;
}
-static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom)
{
return atom->cmd_size;
}
-static void evergreenSendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendTexState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
}
}
-static int check_evergreen_tx(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_evergreen_tx(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
unsigned int i, count = 0;
return count * 37 + 6;
}
-static void evergreenSendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendSQConfig(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
}
extern int evergreen_getTypeSize(GLenum type);
-static void evergreenSetupVTXConstants(GLcontext * ctx,
+static void evergreenSetupVTXConstants(struct gl_context * ctx,
void * pAos,
StreamDesc * pStreamDesc)
{
COMMIT_BATCH();
}
-static int check_evergreen_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_evergreen_vtx(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
int count = context->radeon.tcl.aos_count * 12;
return count;
}
-static void evergreenSendVTX(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendVTX(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *)(context->selected_vp);
}
}
}
-static void evergreenSendPA(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendPA(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
COMMIT_BATCH();
}
-static void evergreenSendTP(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendTP(struct gl_context *ctx, struct radeon_state_atom *atom)
{
/*
context_t *context = EVERGREEN_CONTEXT(ctx);
*/
}
-static void evergreenSendPSresource(GLcontext *ctx)
+static void evergreenSendPSresource(struct gl_context *ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
COMMIT_BATCH();
}
-static void evergreenSendVSresource(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendVSresource(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
COMMIT_BATCH();
}
-static void evergreenSendSQ(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendSQ(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
COMMIT_BATCH();
}
-static void evergreenSendSPI(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendSPI(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
COMMIT_BATCH();
}
-static void evergreenSendSX(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendSX(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
{
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
struct radeon_renderbuffer *rrb;
- unsigned int nPitchInPixel, height;
+ unsigned int nPitchInPixel, height, offtostencil;
rrb = radeon_get_depthbuffer(&context->radeon);
if (!rrb)
SETfield(evergreen->DB_Z_INFO.u32All, ARRAY_1D_TILED_THIN1,
EG_DB_Z_INFO__ARRAY_MODE_shift,
EG_DB_Z_INFO__ARRAY_MODE_mask);
+
+
+ offtostencil = ((height * rrb->pitch) + 255) & ~255;
+ evergreen->DB_STENCIL_WRITE_BASE.u32All = offtostencil >> 8;
+ evergreen->DB_STENCIL_READ_BASE.u32All = offtostencil >> 8;
+
}
-static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendDB(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
struct radeon_renderbuffer *rrb;
- unsigned int zheight, zpitch, offtostencil;
BATCH_LOCALS(&context->radeon);
radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
rrb = radeon_get_depthbuffer(&context->radeon);
- if (context->radeon.radeonScreen->driScreen->dri2.enabled)
- {
- zheight = rrb->base.Height;
- }
- else
- {
- zheight = context->radeon.radeonScreen->driScreen->fbHeight;
- }
- zpitch = rrb->pitch;
-
if( (rrb != NULL) && (rrb->bo != NULL) )
{
//10
if((evergreen->DB_DEPTH_CONTROL.u32All & STENCIL_ENABLE_bit) > 0)
{
- offtostencil = ((zheight * zpitch + 255) >> 8) & 0xffffffff;
BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, offtostencil);
+ EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, evergreen->DB_STENCIL_READ_BASE.u32All);
R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_READ_BASE.u32All,
rrb->bo,
evergreen->DB_STENCIL_READ_BASE.u32All,
END_BATCH();
BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, offtostencil);
+ EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, evergreen->DB_STENCIL_WRITE_BASE.u32All);
R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_WRITE_BASE.u32All,
rrb->bo,
evergreen->DB_STENCIL_WRITE_BASE.u32All,
evergreen->render_target[id].enabled = GL_TRUE;
}
-static void evergreenSendCB(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendCB(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
COMMIT_BATCH();
}
-static void evergreenSendVGT(GLcontext *ctx, struct radeon_state_atom *atom)
+static void evergreenSendVGT(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);