Merge branch 'radeon-texrewrite-clean' into mesa_7_7_branch

[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 47b38d2e36fbda278fcd700c188aef1dc76247ef..2b2b4d748f6c7e74ebf4d49f1316f89ca0f64b22 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -54,11 +54,15 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
        for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
                if (ctx->Texture.Unit[i]._ReallyEnabled) {
                        radeonTexObj *t = r700->textures[i];
+                       uint32_t offset;
                        if (t) {
-                               if (!t->image_override)
+                               if (!t->image_override) {
                                        bo = t->mt->bo;
-                               else
+                                       offset = get_base_teximage_offset(t);
+                               } else {
                                        bo = t->bo;
+                                       offset = 0;
+                               }
                                if (bo) {
 
                                        r700SyncSurf(context, bo,
@@ -77,7 +81,7 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
                                        R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
                                        R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
                                                             bo,
-                                                            0,
+                                                            offset,
                                                             RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
                                        R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
                                                             bo,
@@ -784,8 +788,7 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
        BATCH_LOCALS(&context->radeon);
        radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 
-        BEGIN_BATCH_NO_AUTOSTATE(23);
-       R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All);
+       BEGIN_BATCH_NO_AUTOSTATE(17);
 
        R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
        R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
@@ -798,7 +801,6 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
        R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
        R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
 
-       R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All);
        R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
 
        END_BATCH();
@@ -1282,7 +1284,7 @@ void r600InitAtoms(context_t *context)
        context->radeon.hw.atomlist.name = "atom-list";
 
        ALLOC_STATE(sq, always, 34, r700SendSQConfig);
-       ALLOC_STATE(db, always, 23, r700SendDBState);
+       ALLOC_STATE(db, always, 17, r700SendDBState);
        ALLOC_STATE(stencil, always, 4, r700SendStencilState);
        ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState);
        ALLOC_STATE(sc, always, 15, r700SendSCState);