Merge branch 'radeon-texrewrite-clean' into mesa_7_7_branch

[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 75b97c56cdb919e9091535fb298a6aae369dc4d9..2b2b4d748f6c7e74ebf4d49f1316f89ca0f64b22 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -54,11 +54,15 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
        for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
                if (ctx->Texture.Unit[i]._ReallyEnabled) {
                        radeonTexObj *t = r700->textures[i];
+                       uint32_t offset;
                        if (t) {
-                               if (!t->image_override)
+                               if (!t->image_override) {
                                        bo = t->mt->bo;
-                               else
+                                       offset = get_base_teximage_offset(t);
+                               } else {
                                        bo = t->bo;
+                                       offset = 0;
+                               }
                                if (bo) {
 
                                        r700SyncSurf(context, bo,
@@ -77,7 +81,7 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
                                        R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
                                        R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
                                                             bo,
-                                                            0,
+                                                            offset,
                                                             RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
                                        R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
                                                             bo,
@@ -358,7 +362,6 @@ static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *a
 
        rrb = radeon_get_depthbuffer(&context->radeon);
        if (!rrb || !rrb->bo) {
-               fprintf(stderr, "no rrb\n");
                return;
        }
 
@@ -400,7 +403,6 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *
 
        rrb = radeon_get_colorbuffer(&context->radeon);
        if (!rrb || !rrb->bo) {
-               fprintf(stderr, "no rrb\n");
                return;
        }
 
@@ -786,8 +788,7 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
        BATCH_LOCALS(&context->radeon);
        radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 
-        BEGIN_BATCH_NO_AUTOSTATE(23);
-       R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All);
+       BEGIN_BATCH_NO_AUTOSTATE(17);
 
        R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
        R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
@@ -800,7 +801,6 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
        R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
        R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
 
-       R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All);
        R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
 
        END_BATCH();
@@ -1100,6 +1100,32 @@ static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
        COMMIT_BATCH();
 }
 
+static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+       radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+       struct radeon_query_object *query = radeon->query.current;
+       BATCH_LOCALS(radeon);
+       radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
+
+       /* clear the buffer */
+       radeon_bo_map(query->bo, GL_FALSE);
+       memset(query->bo->ptr, 0, 4 * 2 * sizeof(uint64_t)); /* 4 DBs, 2 qwords each */
+       radeon_bo_unmap(query->bo);
+
+       radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
+                                     query->bo,
+                                     0, RADEON_GEM_DOMAIN_GTT);
+
+       BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
+       R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
+       R600_OUT_BATCH(ZPASS_DONE);
+       R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
+       R600_OUT_BATCH(0x00000000);
+       R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
+       END_BATCH();
+       query->emitted_begin = GL_TRUE;
+}
+
 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 {
        return atom->cmd_size;
@@ -1208,6 +1234,20 @@ static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom)
        return count;
 }
 
+static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom)
+{
+       radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+       struct radeon_query_object *query = radeon->query.current;
+       int count;
+
+       if (!query || query->emitted_begin)
+               count = 0;
+       else
+               count = atom->cmd_size;
+       radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
+       return count;
+}
+
 #define ALLOC_STATE( ATOM, CHK, SZ, EMIT )                             \
 do {                                                                   \
        context->atoms.ATOM.cmd_size = (SZ);                            \
@@ -1221,6 +1261,19 @@ do {                                                                     \
        insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
 } while (0)
 
+static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ)
+{
+       radeon->query.queryobj.cmd_size = (SZ);
+       radeon->query.queryobj.cmd = NULL;
+       radeon->query.queryobj.name = "queryobj";
+       radeon->query.queryobj.idx = 0;
+       radeon->query.queryobj.check = check_queryobj;
+       radeon->query.queryobj.dirty = GL_FALSE;
+       radeon->query.queryobj.emit = r700SendQueryBegin;
+       radeon->hw.max_state_size += (SZ);
+       insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
+}
+
 void r600InitAtoms(context_t *context)
 {
        radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
@@ -1231,7 +1284,7 @@ void r600InitAtoms(context_t *context)
        context->radeon.hw.atomlist.name = "atom-list";
 
        ALLOC_STATE(sq, always, 34, r700SendSQConfig);
-       ALLOC_STATE(db, always, 23, r700SendDBState);
+       ALLOC_STATE(db, always, 17, r700SendDBState);
        ALLOC_STATE(stencil, always, 4, r700SendStencilState);
        ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState);
        ALLOC_STATE(sc, always, 15, r700SendSCState);
@@ -1260,6 +1313,7 @@ void r600InitAtoms(context_t *context)
        ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
        ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
        ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
+       r600_init_query_stateobj(&context->radeon, 6 * 2);
 
        context->radeon.hw.is_dirty = GL_TRUE;
        context->radeon.hw.all_dirty = GL_TRUE;