#include "radeon_mipmap_tree.h"
-static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendTexState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
#define SAMPLER_STRIDE 3
-static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendTexSamplerState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
}
}
-static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendTexBorderColorState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
}
extern int getTypeSize(GLenum type);
-static void r700SetupVTXConstants(GLcontext * ctx,
+static void r700SetupVTXConstants(struct gl_context * ctx,
void * pAos,
StreamDesc * pStreamDesc)
{
}
-static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendVTXState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
struct r700_vertex_program *vp = context->selected_vp;
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM;
struct radeon_renderbuffer *rrb;
- unsigned int nPitchInPixel;
+ unsigned int nPitchInPixel, height;
rrb = radeon_get_colorbuffer(&context->radeon);
if (!rrb || !rrb->bo) {
r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
nPitchInPixel = rrb->pitch/rrb->cpp;
+
+ if (context->radeon.radeonScreen->driScreen->dri2.enabled)
+ {
+ height = rrb->base.Height;
+ }
+ else
+ {
+ height = context->radeon.radeonScreen->driScreen->fbHeight;
+ }
+
SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
- SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
+ SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1,
SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
struct radeon_renderbuffer *rrb;
- unsigned int nPitchInPixel;
+ unsigned int nPitchInPixel, height;
rrb = radeon_get_depthbuffer(&context->radeon);
if (!rrb)
nPitchInPixel = rrb->pitch/rrb->cpp;
+ if (context->radeon.radeonScreen->driScreen->dri2.enabled)
+ {
+ height = rrb->base.Height;
+ }
+ else
+ {
+ height = context->radeon.radeonScreen->driScreen->fbHeight;
+ }
+
SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
- SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
+ SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1,
SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
if(4 == rrb->cpp)
/* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
}
-static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendDepthTargetState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
}
-static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendRenderTargetState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
}
-static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendPSState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
}
-static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendVSState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendFSState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
}
-static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendViewportState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
}
-static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendSQConfig(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendUCPState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
}
}
-static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendSPIState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendVGTState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendSXState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendDBState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendStencilState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendCBState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendCBCLRCMPState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendCBBlendState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendCBBlendColorState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendSUState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
}
-static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendPolyState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
}
-static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendCLState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendGBState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendScissorState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendSCState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendAAState(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendPSConsts(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendVSConsts(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
COMMIT_BATCH();
}
-static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
+static void r700SendQueryBegin(struct gl_context *ctx, struct radeon_state_atom *atom)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct radeon_query_object *query = radeon->query.current;
BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
- R600_OUT_BATCH(ZPASS_DONE);
+ R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
R600_OUT_BATCH(0x00000000);
R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
query->emitted_begin = GL_TRUE;
}
-static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom)
{
return atom->cmd_size;
}
-static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_cb(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
int count = 7;
return count;
}
-static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_blnd(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
return count;
}
-static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_ucp(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
return count;
}
-static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_vtx(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
int count = context->radeon.tcl.aos_count * 18;
return count;
}
-static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_tx(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
unsigned int i, count = 0;
return count * 31;
}
-static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_ps_consts(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
return count;
}
-static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_vs_consts(struct gl_context *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
return count;
}
-static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_queryobj(struct gl_context *ctx, struct radeon_state_atom *atom)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct radeon_query_object *query = radeon->query.current;