Merge commit 'origin/master' into glsl-pp-rework-2

[mesa.git] / src / mesa / drivers / dri / r600 / r700_render.c

diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index cdf3220a7f36df089db84467425e512382c38f01..b1c3648ca568867685e29afac3fb875d97d4a4a8 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -53,6 +53,8 @@
 #include "r700_fragprog.h"
 #include "r700_state.h"
 
+#include "radeon_common_context.h"
+
 void r700WaitForIdle(context_t *context);
 void r700WaitForIdleClean(context_t *context);
 GLboolean r700SendTextureState(context_t *context);
@@ -67,6 +69,7 @@ GLboolean r700SyncSurf(context_t *context,
 void r700WaitForIdle(context_t *context)
 {
     BATCH_LOCALS(&context->radeon);
+    radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
     BEGIN_BATCH_NO_AUTOSTATE(3);
 
     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
@@ -80,6 +83,7 @@ void r700WaitForIdle(context_t *context)
 void r700WaitForIdleClean(context_t *context)
 {
     BATCH_LOCALS(&context->radeon);
+    radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
     BEGIN_BATCH_NO_AUTOSTATE(5);
 
     R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
@@ -96,6 +100,7 @@ void r700WaitForIdleClean(context_t *context)
 void r700Start3D(context_t *context)
 {
     BATCH_LOCALS(&context->radeon);
+    radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
     if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
     {
         BEGIN_BATCH_NO_AUTOSTATE(2);
@@ -122,6 +127,7 @@ GLboolean r700SyncSurf(context_t *context,
                       uint32_t sync_type)
 {
     BATCH_LOCALS(&context->radeon);
+    radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
     uint32_t cp_coher_size;
 
     if (!pbo)
@@ -141,8 +147,7 @@ GLboolean r700SyncSurf(context_t *context,
     R600_OUT_BATCH_RELOC(0,
                         pbo,
                         0,
-                        read_domain, write_domain, 0); // ???
-
+                        read_domain, write_domain, 0);
     END_BATCH();
     COMMIT_BATCH();
 
@@ -252,10 +257,16 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim
        uint32_t vgt_index_type     = 0;
        uint32_t vgt_primitive_type = 0;
        uint32_t vgt_num_indices    = 0;
+       TNLcontext *tnl = TNL_CONTEXT(ctx);
+       struct vertex_buffer *vb = &tnl->vb;
 
        type = r700PrimitiveType(prim);
        num_indices = r700NumVerts(end - start, prim);
 
+       radeon_print(RADEON_RENDER, RADEON_TRACE,
+               "%s type %x num_indices %d\n",
+               __func__, type, num_indices);
+
        if (type < 0 || num_indices <= 0)
                return;
 
@@ -291,29 +302,60 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim
         R600_OUT_BATCH(vgt_draw_initiator);
 
         for (i = start; i < (start + num_indices); i++) {
-            R600_OUT_BATCH(i);
+               if(vb->Elts)
+                       R600_OUT_BATCH(vb->Elts[i]);
+               else
+                       R600_OUT_BATCH(i);
         }
         END_BATCH();
         COMMIT_BATCH();
 
 }
 
+/* start 3d, idle, cb/db flush */
+#define PRE_EMIT_STATE_BUFSZ 10 + 5 + 14
+
+static GLuint r700PredictRenderSize(GLcontext* ctx)
+{
+    context_t *context = R700_CONTEXT(ctx);
+    TNLcontext *tnl = TNL_CONTEXT(ctx);
+    struct r700_vertex_program *vp = context->selected_vp;
+    struct vertex_buffer *vb = &tnl->vb;
+    GLboolean flushed;
+    GLuint dwords, i;
+    GLuint state_size;
+    /* pre calculate aos count so state prediction works */
+    context->radeon.tcl.aos_count = _mesa_bitcount(vp->mesa_program->Base.InputsRead);
+
+    dwords = PRE_EMIT_STATE_BUFSZ;
+    for (i = 0; i < vb->PrimitiveCount; i++)
+        dwords += vb->Primitive[i].count + 10;
+    state_size = radeonCountStateEmitSize(&context->radeon);
+    flushed = rcommonEnsureCmdBufSpace(&context->radeon,
+            dwords + state_size, __FUNCTION__);
+
+    if (flushed)
+        dwords += radeonCountStateEmitSize(&context->radeon);
+    else
+        dwords += state_size;
+
+    radeon_print(RADEON_RENDER, RADEON_VERBOSE,
+       "%s: total prediction size is %d.\n", __FUNCTION__, dwords);
+    return dwords;
+}
+
 static GLboolean r700RunRender(GLcontext * ctx,
                               struct tnl_pipeline_stage *stage)
 {
     context_t *context = R700_CONTEXT(ctx);
     radeonContextPtr radeon = &context->radeon;
-    unsigned int i, ind_count = 0, id = 0;
+    unsigned int i, id = 0;
     TNLcontext *tnl = TNL_CONTEXT(ctx);
     struct vertex_buffer *vb = &tnl->vb;
     struct radeon_renderbuffer *rrb;
 
-    for (i = 0; i < vb->PrimitiveCount; i++)
-           ind_count += vb->Primitive[i].count + 10;
-
-    /* just an estimate, need to properly calculate this */
-    rcommonEnsureCmdBufSpace(&context->radeon,
-                            radeon->hw.max_state_size + ind_count, __FUNCTION__);
+    radeon_print(RADEON_RENDER, RADEON_NORMAL, "%s: cs begin at %d\n",
+                __func__, context->radeon.cmdbuf.cs->cdw);
 
     /* always emit CB base to prevent
      * lock ups on some chips.
@@ -322,22 +364,26 @@ static GLboolean r700RunRender(GLcontext * ctx,
     /* mark vtx as dirty since it changes per-draw */
     R600_STATECHANGE(context, vtx);
 
-    r700UpdateShaders(ctx);
     r700SetScissor(context);
     r700SetupVertexProgram(ctx);
     r700SetupFragmentProgram(ctx);
     r600UpdateTextureState(ctx);
+
+    GLuint emit_end = r700PredictRenderSize(ctx) 
+        + context->radeon.cmdbuf.cs->cdw;
     r700SetupStreams(ctx);
 
     radeonEmitState(radeon);
 
+    radeon_debug_add_indent();
     /* richard test code */
     for (i = 0; i < vb->PrimitiveCount; i++) {
         GLuint prim = _tnl_translate_prim(&vb->Primitive[i]);
         GLuint start = vb->Primitive[i].start;
         GLuint end = vb->Primitive[i].start + vb->Primitive[i].count;
-       r700RunRenderPrimitive(ctx, start, end, prim);
+        r700RunRenderPrimitive(ctx, start, end, prim);
     }
+    radeon_debug_remove_indent();
 
     /* Flush render op cached for last several quads. */
     r700WaitForIdleClean(context);
@@ -354,6 +400,13 @@ static GLboolean r700RunRender(GLcontext * ctx,
 
     radeonReleaseArrays(ctx, ~0);
 
+    radeon_print(RADEON_RENDER, RADEON_TRACE, "%s: cs end at %d\n",
+                __func__, context->radeon.cmdbuf.cs->cdw);
+
+    if ( emit_end < context->radeon.cmdbuf.cs->cdw )
+       WARN_ONCE("Rendering was %d commands larger than predicted size."
+              " We might overflow  command buffer.\n", context->radeon.cmdbuf.cs->cdw - emit_end);
+
     return GL_FALSE;
 }
 
@@ -372,7 +425,10 @@ static GLboolean r700RunTCLRender(GLcontext * ctx,  /*----------------------*/
 
     /* TODO : sw fallback */
 
+    /* Need shader bo's setup before bo check */
+    r700UpdateShaders(ctx);
     /**
+
     * Ensure all enabled and complete textures are uploaded along with any buffers being used.
     */
     if(!r600ValidateBuffers(ctx))