static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim)
{
- context_t *context = R700_CONTEXT(ctx);
- BATCH_LOCALS(&context->radeon);
- int type, i, total_emit;
- int num_indices;
- uint32_t vgt_draw_initiator = 0;
- uint32_t vgt_index_type = 0;
- uint32_t vgt_primitive_type = 0;
- uint32_t vgt_num_indices = 0;
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- struct vertex_buffer *vb = &tnl->vb;
-
- type = r700PrimitiveType(prim);
- num_indices = r700NumVerts(end - start, prim);
-
- radeon_print(RADEON_RENDER, RADEON_TRACE,
- "%s type %x num_indices %d\n",
- __func__, type, num_indices);
-
- if (type < 0 || num_indices <= 0)
- return;
+ context_t *context = R700_CONTEXT(ctx);
+ BATCH_LOCALS(&context->radeon);
+ int type, total_emit;
+ int num_indices;
+ uint32_t vgt_draw_initiator = 0;
+ uint32_t vgt_index_type = 0;
+ uint32_t vgt_primitive_type = 0;
+ uint32_t vgt_num_indices = 0;
+ GLboolean bUseDrawIndex;
+
+ if(NULL != context->ind_buf.bo)
+ {
+ bUseDrawIndex = GL_TRUE;
+ }
+ else
+ {
+ bUseDrawIndex = GL_FALSE;
+ }
+
+ type = r700PrimitiveType(prim);
+ num_indices = r700NumVerts(end - start, prim);
+
+ radeon_print(RADEON_RENDER, RADEON_TRACE,
+ "%s type %x num_indices %d\n",
+ __func__, type, num_indices);
- total_emit = 3 /* VGT_PRIMITIVE_TYPE */
- + 2 /* VGT_INDEX_TYPE */
- + 2 /* NUM_INSTANCES */
- + num_indices + 3; /* DRAW_INDEX_IMMD */
+ if (type < 0 || num_indices <= 0)
+ return;
+
+ if(GL_TRUE == bUseDrawIndex)
+ {
+ total_emit = 3 /* VGT_PRIMITIVE_TYPE */
+ + 2 /* VGT_INDEX_TYPE */
+ + 2 /* NUM_INSTANCES */
+ + 3 /* VGT_INDEX_OFFSET */
+ + 5 + 2; /* DRAW_INDEX */
+ }
+ else
+ {
+ total_emit = 3 /* VGT_PRIMITIVE_TYPE */
+ + 2 /* VGT_INDEX_TYPE */
+ + 2 /* NUM_INSTANCES */
+ + 3 /* VGT_INDEX_OFFSET */
+ + 3; /* DRAW_INDEX_AUTO */
+ }
BEGIN_BATCH_NO_AUTOSTATE(total_emit);
- // prim
+ // prim
SETfield(vgt_primitive_type, type,
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
+ VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX);
R600_OUT_BATCH(vgt_primitive_type);
// index type
SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
+
+ if(GL_TRUE == bUseDrawIndex)
+ {
+ if(GL_TRUE != context->ind_buf.is_32bit)
+ {
+ SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
+ }
+ }
+
R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
R600_OUT_BATCH(vgt_index_type);
- // num instances
- R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
- R600_OUT_BATCH(1);
+ // num instances
+ R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
+ R600_OUT_BATCH(1);
- // draw packet
+ // draw packet
vgt_num_indices = num_indices;
- SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
- SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1)));
- R600_OUT_BATCH(vgt_num_indices);
- R600_OUT_BATCH(vgt_draw_initiator);
+ if(GL_TRUE == bUseDrawIndex)
+ {
+ SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
+ }
+ else
+ {
+ SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
+ }
+
+ SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
- if(NULL == context->ind_buf.bo)
+ if(GL_TRUE == bUseDrawIndex)
{
- for (i = start; i < (start + num_indices); i++) {
- if(vb->Elts)
- {
- R600_OUT_BATCH(vb->Elts[i]);
- }
- else
- R600_OUT_BATCH(i);
- }
+ R600_OUT_BATCH_REGSEQ(VGT_INDX_OFFSET, 1);
+ R600_OUT_BATCH(0);
+ R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3));
+ R600_OUT_BATCH(context->ind_buf.bo_offset);
+ R600_OUT_BATCH(0);
+ R600_OUT_BATCH(vgt_num_indices);
+ R600_OUT_BATCH(vgt_draw_initiator);
+ R600_OUT_BATCH_RELOC(context->ind_buf.bo_offset,
+ context->ind_buf.bo,
+ context->ind_buf.bo_offset,
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
}
else
- {
- if(GL_TRUE == context->ind_buf.bHostIb)
- {
- if(GL_TRUE != context->ind_buf.is_32bit)
- {
- GLushort * pIndex = (GLushort*)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
- pIndex += start;
- for (i = 0; i < num_indices; i++)
- {
- R600_OUT_BATCH(*pIndex);
- pIndex++;
- }
- }
- else
- {
- GLuint * pIndex = (GLuint*)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
- pIndex += start;
-
- for (i = 0; i < num_indices; i++)
- {
- R600_OUT_BATCH(*pIndex);
- pIndex++;
- }
- }
- }
- else
- {
- /* TODO : hw ib draw */
- }
+ {
+ R600_OUT_BATCH_REGSEQ(VGT_INDX_OFFSET, 1);
+ R600_OUT_BATCH(start);
+ R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO,1));
+ R600_OUT_BATCH(vgt_num_indices);
+ R600_OUT_BATCH(vgt_draw_initiator);
}
END_BATCH();
/* start 3d, idle, cb/db flush */
#define PRE_EMIT_STATE_BUFSZ 10 + 5 + 14
-static GLuint r700PredictRenderSize(GLcontext* ctx)
+static GLuint r700PredictRenderSize(GLcontext* ctx,
+ const struct _mesa_prim *prim,
+ const struct _mesa_index_buffer *ib,
+ GLuint nr_prims)
{
context_t *context = R700_CONTEXT(ctx);
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- struct r700_vertex_program *vp = context->selected_vp;
- struct vertex_buffer *vb = &tnl->vb;
GLboolean flushed;
GLuint dwords, i;
GLuint state_size;
- /* pre calculate aos count so state prediction works */
- context->radeon.tcl.aos_count = _mesa_bitcount(vp->mesa_program->Base.InputsRead);
dwords = PRE_EMIT_STATE_BUFSZ;
- for (i = 0; i < vb->PrimitiveCount; i++)
- dwords += vb->Primitive[i].count + 10;
+ if (ib)
+ dwords += nr_prims * 17;
+ else {
+ for (i = 0; i < nr_prims; ++i)
+ {
+ dwords += 13;
+ }
+ }
+
state_size = radeonCountStateEmitSize(&context->radeon);
flushed = rcommonEnsureCmdBufSpace(&context->radeon,
- dwords + state_size, __FUNCTION__);
-
+ dwords + state_size,
+ __FUNCTION__);
if (flushed)
- dwords += radeonCountStateEmitSize(&context->radeon);
+ dwords += radeonCountStateEmitSize(&context->radeon);
else
- dwords += state_size;
+ dwords += state_size;
- radeon_print(RADEON_RENDER, RADEON_VERBOSE,
- "%s: total prediction size is %d.\n", __FUNCTION__, dwords);
+ radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: total prediction size is %d.\n", __FUNCTION__, dwords);
return dwords;
-}
-
-static GLboolean r700RunRender(GLcontext * ctx,
- struct tnl_pipeline_stage *stage)
-{
- context_t *context = R700_CONTEXT(ctx);
- radeonContextPtr radeon = &context->radeon;
- unsigned int i, id = 0;
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- struct vertex_buffer *vb = &tnl->vb;
- struct radeon_renderbuffer *rrb;
-
- radeon_print(RADEON_RENDER, RADEON_NORMAL, "%s: cs begin at %d\n",
- __func__, context->radeon.cmdbuf.cs->cdw);
-
- /* always emit CB base to prevent
- * lock ups on some chips.
- */
- R600_STATECHANGE(context, cb_target);
- /* mark vtx as dirty since it changes per-draw */
- R600_STATECHANGE(context, vtx);
-
- r700SetScissor(context);
- r700SetupVertexProgram(ctx);
- r700SetupFragmentProgram(ctx);
- r600UpdateTextureState(ctx);
-
- GLuint emit_end = r700PredictRenderSize(ctx)
- + context->radeon.cmdbuf.cs->cdw;
- r700SetupStreams(ctx);
-
- radeonEmitState(radeon);
-
- radeon_debug_add_indent();
- /* richard test code */
- for (i = 0; i < vb->PrimitiveCount; i++) {
- GLuint prim = _tnl_translate_prim(&vb->Primitive[i]);
- GLuint start = vb->Primitive[i].start;
- GLuint end = vb->Primitive[i].start + vb->Primitive[i].count;
- r700RunRenderPrimitive(ctx, start, end, prim);
- }
- radeon_debug_remove_indent();
-
- /* Flush render op cached for last several quads. */
- r700WaitForIdleClean(context);
-
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (rrb && rrb->bo)
- r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
- CB_ACTION_ENA_bit | (1 << (id + 6)));
- rrb = radeon_get_depthbuffer(&context->radeon);
- if (rrb && rrb->bo)
- r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
- DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit);
-
- radeonReleaseArrays(ctx, ~0);
-
- radeon_print(RADEON_RENDER, RADEON_TRACE, "%s: cs end at %d\n",
- __func__, context->radeon.cmdbuf.cs->cdw);
-
- if ( emit_end < context->radeon.cmdbuf.cs->cdw )
- WARN_ONCE("Rendering was %d commands larger than predicted size."
- " We might overflow command buffer.\n", context->radeon.cmdbuf.cs->cdw - emit_end);
-
- return GL_FALSE;
-}
-
-static GLboolean r700RunNonTCLRender(GLcontext * ctx,
- struct tnl_pipeline_stage *stage) /* -------------------- */
-{
- GLboolean bRet = GL_TRUE;
-
- return bRet;
-}
-
-static GLboolean r700RunTCLRender(GLcontext * ctx, /*----------------------*/
- struct tnl_pipeline_stage *stage)
-{
- GLboolean bRet = GL_FALSE;
-
- /* TODO : sw fallback */
-
- /* Need shader bo's setup before bo check */
- r700UpdateShaders(ctx);
- /**
-
- * Ensure all enabled and complete textures are uploaded along with any buffers being used.
- */
- if(!r600ValidateBuffers(ctx))
- {
- return GL_TRUE;
- }
-
- bRet = r700RunRender(ctx, stage);
-
- return bRet;
- //GL_FALSE will stop to do other pipe stage in _tnl_run_pipeline
- //The render here DOES finish the whole pipe, so GL_FALSE should be returned for success.
}
-const struct tnl_pipeline_stage _r700_render_stage = {
- "r700 Hardware Rasterization",
- NULL,
- NULL,
- NULL,
- NULL,
- r700RunNonTCLRender
-};
-
-const struct tnl_pipeline_stage _r700_tcl_stage = {
- "r700 Hardware Transform, Clipping and Lighting",
- NULL,
- NULL,
- NULL,
- NULL,
- r700RunTCLRender
-};
-
-const struct tnl_pipeline_stage *r700_pipeline[] =
-{
- &_r700_tcl_stage,
- &_tnl_vertex_transform_stage,
- &_tnl_normal_transform_stage,
- &_tnl_lighting_stage,
- &_tnl_fog_coordinate_stage,
- &_tnl_texgen_stage,
- &_tnl_texture_transform_stage,
- &_tnl_vertex_program_stage,
-
- &_r700_render_stage,
- &_tnl_render_stage,
- 0,
-};
-
#define CONVERT( TYPE, MACRO ) do { \
GLuint i, j, sz; \
sz = input->Size; \
attr->stride = dst_stride;
}
-static void r700SetupStreams2(GLcontext *ctx, const struct gl_client_array *input[], int count)
+static void r700SetupStreams(GLcontext *ctx, const struct gl_client_array *input[], int count)
{
context_t *context = R700_CONTEXT(ctx);
GLuint stride;
{
case 1:
radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- context->stream_desc[index].stride = 4;
break;
case 2:
radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- context->stream_desc[index].stride = 8;
break;
case 3:
radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- context->stream_desc[index].stride = 12;
break;
case 4:
radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- context->stream_desc[index].stride = 16;
break;
default:
assert(0);
}
}
- context->radeon.tcl.aos_count = context->nNumActiveAos;
ret = radeon_cs_space_check_with_bo(context->radeon.cmdbuf.cs,
first_elem(&context->radeon.dma.reserved)->bo,
RADEON_GEM_DOMAIN_GTT, 0);
* called during context destroy
*/
context_t *context = R700_CONTEXT(ctx);
-
+
int i;
- for (i = 0; i < context->nNumActiveAos; i++)
+ for (i = 0; i < context->nNumActiveAos; i++)
{
- if (!context->stream_desc[i].is_named_bo)
+ if (!context->stream_desc[i].is_named_bo)
{
radeon_bo_unref(context->stream_desc[i].bo);
}
context->radeon.tcl.aos[i].bo = NULL;
}
-
- if (context->ind_buf.bo != NULL)
+
+ if (context->ind_buf.bo != NULL)
{
- if(context->ind_buf.bHostIb != GL_TRUE)
- {
radeon_bo_unref(context->ind_buf.bo);
- }
- else
- {
- FREE(context->ind_buf.bo->ptr);
- FREE(context->ind_buf.bo);
- context->ind_buf.bo = NULL;
- }
}
}
int i;
GLboolean mapped_named_bo = GL_FALSE;
- if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
+ if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
{
ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj);
mapped_named_bo = GL_TRUE;
}
src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
- if (mesa_ind_buf->type == GL_UNSIGNED_BYTE)
+ if (mesa_ind_buf->type == GL_UNSIGNED_BYTE)
{
GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
GLubyte *in = (GLubyte *)src_ptr;
- if(context->ind_buf.bHostIb != GL_TRUE)
- {
- radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
- &context->ind_buf.bo_offset, size, 4);
+ radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
+ &context->ind_buf.bo_offset, size, 4);
- assert(context->ind_buf.bo->ptr != NULL);
- out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
- }
- else
- {
- context->ind_buf.bo = MALLOC_STRUCT(radeon_bo);
- context->ind_buf.bo->ptr = ALIGN_MALLOC(size, 4);
- context->ind_buf.bo_offset = 0;
- out = (GLuint *)context->ind_buf.bo->ptr;
- }
+ assert(context->ind_buf.bo->ptr != NULL);
+ out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
- for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
+ for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
{
*out++ = in[i] | in[i + 1] << 16;
}
- if (i < mesa_ind_buf->count)
+ if (i < mesa_ind_buf->count)
{
*out++ = in[i];
}
#if MESA_BIG_ENDIAN
- }
- else
+ }
+ else
{ /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
GLushort *in = (GLushort *)src_ptr;
GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
- if(context->ind_buf.bHostIb != GL_TRUE)
- {
- radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
- &context->ind_buf.bo_offset, size, 4);
+ radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
+ &context->ind_buf.bo_offset, size, 4);
- assert(context->ind_buf.bo->ptr != NULL);
- out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
- }
- else
- {
- context->ind_buf.bo = MALLOC_STRUCT(radeon_bo);
- context->ind_buf.bo->ptr = ALIGN_MALLOC(size, 4);
- context->ind_buf.bo_offset = 0;
- out = (GLuint *)context->ind_buf.bo->ptr;
- }
+ assert(context->ind_buf.bo->ptr != NULL);
+ out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
- for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
+ for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
{
*out++ = in[i] | in[i + 1] << 16;
}
- if (i < mesa_ind_buf->count)
+ if (i < mesa_ind_buf->count)
{
*out++ = in[i];
}
context->ind_buf.is_32bit = GL_FALSE;
context->ind_buf.count = mesa_ind_buf->count;
- if (mapped_named_bo)
+ if (mapped_named_bo)
{
ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj);
}
return;
}
- context->ind_buf.bHostIb = GL_TRUE;
-
#if MESA_BIG_ENDIAN
- if (mesa_ind_buf->type == GL_UNSIGNED_INT)
+ if (mesa_ind_buf->type == GL_UNSIGNED_INT)
{
#else
- if (mesa_ind_buf->type != GL_UNSIGNED_BYTE)
+ if (mesa_ind_buf->type != GL_UNSIGNED_BYTE)
{
#endif
const GLvoid *src_ptr;
GLvoid *dst_ptr;
GLboolean mapped_named_bo = GL_FALSE;
- if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
+ if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
{
ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj);
assert(mesa_ind_buf->obj->Pointer != NULL);
const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type);
- if(context->ind_buf.bHostIb != GL_TRUE)
- {
- radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
- &context->ind_buf.bo_offset, size, 4);
- assert(context->ind_buf.bo->ptr != NULL);
- dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
- }
- else
- {
- context->ind_buf.bo = MALLOC_STRUCT(radeon_bo);
- context->ind_buf.bo->ptr = ALIGN_MALLOC(size, 4);
- context->ind_buf.bo_offset = 0;
- dst_ptr = context->ind_buf.bo->ptr;
- }
+ radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
+ &context->ind_buf.bo_offset, size, 4);
+ assert(context->ind_buf.bo->ptr != NULL);
+ dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
_mesa_memcpy(dst_ptr, src_ptr, size);
context->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT);
context->ind_buf.count = mesa_ind_buf->count;
- if (mapped_named_bo)
+ if (mapped_named_bo)
{
ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj);
}
- }
- else
+ }
+ else
{
r700FixupIndexBuffer(ctx, mesa_ind_buf);
}
}
static GLboolean r700TryDrawPrims(GLcontext *ctx,
- const struct gl_client_array *arrays[],
- const struct _mesa_prim *prim,
- GLuint nr_prims,
- const struct _mesa_index_buffer *ib,
- GLuint min_index,
- GLuint max_index )
+ const struct gl_client_array *arrays[],
+ const struct _mesa_prim *prim,
+ GLuint nr_prims,
+ const struct _mesa_index_buffer *ib,
+ GLuint min_index,
+ GLuint max_index )
{
context_t *context = R700_CONTEXT(ctx);
radeonContextPtr radeon = &context->radeon;
GLuint i, id = 0;
- GLboolean bValidedbuffer;
struct radeon_renderbuffer *rrb;
if (ctx->NewState)
- {
_mesa_update_state( ctx );
- }
- bValidedbuffer = r600ValidateBuffers(ctx);
+ _tnl_UpdateFixedFunctionProgram(ctx);
+ r700SetVertexFormat(ctx, arrays, max_index + 1);
+ /* shaders need to be updated before buffers are validated */
+ r700UpdateShaders(ctx);
+ if (!r600ValidateBuffers(ctx))
+ return GL_FALSE;
/* always emit CB base to prevent
* lock ups on some chips.
/* mark vtx as dirty since it changes per-draw */
R600_STATECHANGE(context, vtx);
- _tnl_UpdateFixedFunctionProgram(ctx);
- r700SetVertexFormat(ctx, arrays, max_index + 1);
- r700SetupStreams2(ctx, arrays, max_index + 1);
- r700UpdateShaders2(ctx);
-
r700SetScissor(context);
-
r700SetupVertexProgram(ctx);
-
r700SetupFragmentProgram(ctx);
-
r600UpdateTextureState(ctx);
- GLuint emit_end = r700PredictRenderSize(ctx)
+ GLuint emit_end = r700PredictRenderSize(ctx, prim, ib, nr_prims)
+ context->radeon.cmdbuf.cs->cdw;
r700SetupIndexBuffer(ctx, ib);
+ r700SetupStreams(ctx, arrays, max_index + 1);
radeonEmitState(radeon);
- for (i = 0; i < nr_prims; ++i)
+ radeon_debug_add_indent();
+ for (i = 0; i < nr_prims; ++i)
{
- r700RunRenderPrimitive(ctx,
- prim[i].start,
- prim[i].start + prim[i].count,
+ r700RunRenderPrimitive(ctx,
+ prim[i].start,
+ prim[i].start + prim[i].count,
prim[i].mode);
}
-
+ radeon_debug_remove_indent();
+
/* Flush render op cached for last several quads. */
r700WaitForIdleClean(context);
return GL_TRUE;
}
-static void r700DrawPrimsRe(GLcontext *ctx,
- const struct gl_client_array *arrays[],
- const struct _mesa_prim *prim,
- GLuint nr_prims,
- const struct _mesa_index_buffer *ib,
- GLboolean index_bounds_valid,
- GLuint min_index,
- GLuint max_index)
+static void r700DrawPrims(GLcontext *ctx,
+ const struct gl_client_array *arrays[],
+ const struct _mesa_prim *prim,
+ GLuint nr_prims,
+ const struct _mesa_index_buffer *ib,
+ GLboolean index_bounds_valid,
+ GLuint min_index,
+ GLuint max_index)
{
- GLboolean retval = GL_FALSE;
+ GLboolean retval = GL_FALSE;
- /* This check should get folded into just the places that
+ /* This check should get folded into just the places that
* min/max index are really needed.
*/
if (!index_bounds_valid) {
}
if (min_index) {
- vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r700DrawPrimsRe );
+ vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r700DrawPrims );
return;
}
_tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
}
-static void r700DrawPrims(GLcontext *ctx,
- const struct gl_client_array *arrays[],
- const struct _mesa_prim *prim,
- GLuint nr_prims,
- const struct _mesa_index_buffer *ib,
- GLboolean index_bounds_valid,
- GLuint min_index,
- GLuint max_index)
-{
- context_t *context = R700_CONTEXT(ctx);
-
- /* For non indexed drawing, using tnl pipe. */
- if(!ib)
- {
- context->ind_buf.bo = NULL;
-
- _tnl_vbo_draw_prims(ctx, arrays, prim, nr_prims, ib,
- index_bounds_valid, min_index, max_index);
- return;
- }
-
- r700DrawPrimsRe(ctx, arrays, prim, nr_prims, ib, index_bounds_valid, min_index, max_index);
-}
-
void r700InitDraw(GLcontext *ctx)
{
struct vbo_context *vbo = vbo_context(ctx);
+ /* to be enabled */
vbo->draw_prims = r700DrawPrims;
}
projects / mesa.git / blobdiff