Merge branch 'gallium-vertexelementcso'
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
index 20e8afefbaa4a44ea17f0f301a3d0eac3f575e8e..6f156b54096fbcdb0f2876217a3c92b618cddbd6 100644 (file)
@@ -26,7 +26,6 @@
 
 #include "main/glheader.h"
 #include "main/mtypes.h"
-#include "main/state.h"
 #include "main/imports.h"
 #include "main/enums.h"
 #include "main/macros.h"
 
 #include "tnl/tnl.h"
 #include "tnl/t_pipeline.h"
-#include "tnl/t_vp_build.h"
 #include "swrast/swrast.h"
 #include "swrast_setup/swrast_setup.h"
 #include "main/api_arrayelt.h"
-#include "main/state.h"
 #include "main/framebuffer.h"
 
 #include "shader/prog_parameter.h"
@@ -68,7 +65,7 @@ void r700UpdateShaders(GLcontext * ctx)
     /* should only happenen once, just after context is created */
     /* TODO: shouldn't we fallback to sw here? */
     if (!ctx->FragmentProgram._Current) {
-           _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
+           fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
            return;
     }
 
@@ -914,10 +911,12 @@ static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa
        case GL_POINT_SIZE_MIN:
                SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
                         MIN_SIZE_shift, MIN_SIZE_mask);
+               r700PointSize(ctx, ctx->Point.Size);
                break;
        case GL_POINT_SIZE_MAX:
                SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
                         MAX_SIZE_shift, MAX_SIZE_mask);
+               r700PointSize(ctx, ctx->Point.Size);
                break;
        case GL_POINT_DISTANCE_ATTENUATION:
                break;
@@ -1629,8 +1628,6 @@ void r700InitState(GLcontext * ctx) //-------------------
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
     int id = 0;
 
-    radeon_firevertices(&context->radeon);
-
     r700->TA_CNTL_AUX.u32All = 0;
     SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
     r700->VC_ENHANCE.u32All = 0;