i965: Add all device ids for sandybridge

[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 6f156b54096fbcdb0f2876217a3c92b618cddbd6..925b4ffe6dd1e2f0485ff2e3b4188841c73c37ba 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -39,9 +39,10 @@
 #include "swrast_setup/swrast_setup.h"
 #include "main/api_arrayelt.h"
 #include "main/framebuffer.h"
+#include "drivers/common/meta.h"
 
-#include "shader/prog_parameter.h"
-#include "shader/prog_statevars.h"
+#include "program/prog_parameter.h"
+#include "program/prog_statevars.h"
 #include "vbo/vbo.h"
 
 #include "r600_context.h"
@@ -252,12 +253,15 @@ void r700UpdateShaderStates(GLcontext * ctx)
 
 static void r700SetDepthState(GLcontext * ctx)
 {
+       struct radeon_renderbuffer *rrb;
        context_t *context = R700_CONTEXT(ctx);
        R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
        R600_STATECHANGE(context, db);
 
-    if (ctx->Depth.Test)
+       rrb = radeon_get_depthbuffer(&context->radeon);
+
+    if (ctx->Depth.Test && rrb && rrb->bo)
     {
         SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
         if (ctx->Depth.Mask)
@@ -614,7 +618,7 @@ static GLuint translate_logicop(GLenum logicop)
        case GL_XOR:
                return 0x66;
        case GL_EQUIV:
-               return 0xaa;
+               return 0x99;
        case GL_AND_REVERSE:
                return 0x44;
        case GL_AND_INVERTED:
@@ -1576,7 +1580,16 @@ static void r700InitSQConfig(GLcontext * ctx)
            CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
     else
            SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
-    SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
+
+    if(GL_TRUE == r700->bShaderUseMemConstant)
+    {
+        CLEARbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
+    }
+    else
+    {
+        SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
+    }
+
     SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
     SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
     SETfield(r700->sq_config.SQ_CONFIG.u32All, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
@@ -1685,8 +1698,9 @@ void r700InitState(GLcontext * ctx) //-------------------
            SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
     }
 
-    /* Do scale XY and Z by 1/W0. */
-    r700->bEnablePerspective = GL_TRUE;
+    /* Do scale XY and Z by 1/W0. */   
+    r700->bEnablePerspective = GL_TRUE;    
+
     CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
     CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
     SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
@@ -1816,7 +1830,7 @@ void r700InitState(GLcontext * ctx) //-------------------
 
 }
 
-void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
+void r700InitStateFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
 {
        functions->UpdateState = r700InvalidateState;
        functions->AlphaFunc = r700AlphaFunc;
@@ -1857,8 +1871,12 @@ void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
 
        functions->Scissor = radeonScissor;
 
-       functions->DrawBuffer           = radeonDrawBuffer;
-       functions->ReadBuffer           = radeonReadBuffer;
+       functions->DrawBuffer = radeonDrawBuffer;
+       functions->ReadBuffer = radeonReadBuffer;
 
+       functions->CopyPixels = _mesa_meta_CopyPixels;
+       functions->DrawPixels = _mesa_meta_DrawPixels;
+       if (radeon->radeonScreen->kernel_mm)
+               functions->ReadPixels = radeonReadPixels;
 }