static void radeonWaitForIdle(radeonContextPtr radeon)
{
- LOCK_HARDWARE(radeon);
- radeonWaitForIdleLocked(radeon);
- UNLOCK_HARDWARE(radeon);
+ if (!radeon->radeonScreen->driScreen->dri2.enabled) {
+ LOCK_HARDWARE(radeon);
+ radeonWaitForIdleLocked(radeon);
+ UNLOCK_HARDWARE(radeon);
+ }
}
static void radeon_flip_renderbuffers(struct radeon_framebuffer *rfb)
*/
void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
{
- radeonContextPtr radeon = RADEON_CONTEXT(ctx);
-
if (RADEON_DEBUG & DEBUG_DRI)
fprintf(stderr, "%s %s\n", __FUNCTION__,
_mesa_lookup_enum_by_nr( mode ));
- radeon_firevertices(radeon); /* don't pipeline cliprect changes */
-
radeon_draw_buffer(ctx, ctx->DrawBuffer);
}
radeon_window_moved(radeon);
radeon_draw_buffer(ctx, radeon->glCtx->DrawBuffer);
ctx->Driver.Viewport = old_viewport;
-
-
}
-static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state_atom *state )
-{
- int i;
- int dwords = (*state->check)(radeon->glCtx, state);
-
- fprintf(stderr, "emit %s %d/%d\n", state->name, state->cmd_size, dwords);
- if (RADEON_DEBUG & DEBUG_VERBOSE)
- for (i = 0 ; i < dwords; i++)
- fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]);
+static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state_atom *state)
+{
+ int i, j, reg;
+ int dwords = (*state->check) (radeon->glCtx, state);
+ drm_r300_cmd_header_t cmd;
+
+ fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size);
+
+ if (RADEON_DEBUG & DEBUG_VERBOSE) {
+ for (i = 0; i < dwords;) {
+ cmd = *((drm_r300_cmd_header_t *) &state->cmd[i]);
+ reg = (cmd.packet0.reghi << 8) | cmd.packet0.reglo;
+ fprintf(stderr, " %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n",
+ state->name, i, reg, cmd.packet0.count);
+ ++i;
+ for (j = 0; j < cmd.packet0.count && i < dwords; j++) {
+ fprintf(stderr, " %s[%d]: 0x%04x = %08x\n",
+ state->name, i, reg, state->cmd[i]);
+ reg += 4;
+ ++i;
+ }
+ }
+ }
+}
+static void radeon_print_state_atom_kmm(radeonContextPtr radeon, struct radeon_state_atom *state)
+{
+ int i, j, reg, count;
+ int dwords = (*state->check) (radeon->glCtx, state);
+ uint32_t packet0;
+
+ fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size);
+
+ if (RADEON_DEBUG & DEBUG_VERBOSE) {
+ for (i = 0; i < dwords;) {
+ packet0 = state->cmd[i];
+ reg = (packet0 & 0x1FFF) << 2;
+ count = ((packet0 & 0x3FFF0000) >> 16) + 1;
+ fprintf(stderr, " %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n",
+ state->name, i, reg, count);
+ ++i;
+ for (j = 0; j < count && i < dwords; j++) {
+ fprintf(stderr, " %s[%d]: 0x%04x = %08x\n",
+ state->name, i, reg, state->cmd[i]);
+ reg += 4;
+ ++i;
+ }
+ }
+ }
}
static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty)
dwords = (*atom->check) (radeon->glCtx, atom);
if (dwords) {
if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
- radeon_print_state_atom(radeon, atom);
+ if (radeon->radeonScreen->kernel_mm)
+ radeon_print_state_atom_kmm(radeon, atom);
+ else
+ radeon_print_state_atom(radeon, atom);
}
if (atom->emit) {
(*atom->emit)(radeon->glCtx, atom);
COMMIT_BATCH();
}
+GLboolean radeon_revalidate_bos(GLcontext *ctx)
+{
+ radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+ int flushed = 0;
+ int ret;
+again:
+ ret = radeon_cs_space_check(radeon->cmdbuf.cs, radeon->state.bos, radeon->state.validated_bo_count);
+ if (ret == RADEON_CS_SPACE_OP_TO_BIG)
+ return GL_FALSE;
+ if (ret == RADEON_CS_SPACE_FLUSH) {
+ radeonFlush(ctx);
+ if (flushed)
+ return GL_FALSE;
+ flushed = 1;
+ goto again;
+ }
+ return GL_TRUE;
+}
+
+void radeon_validate_reset_bos(radeonContextPtr radeon)
+{
+ int i;
+
+ for (i = 0; i < radeon->state.validated_bo_count; i++) {
+ radeon_bo_unref(radeon->state.bos[i].bo);
+ radeon->state.bos[i].bo = NULL;
+ radeon->state.bos[i].read_domains = 0;
+ radeon->state.bos[i].write_domain = 0;
+ radeon->state.bos[i].new_accounted = 0;
+ }
+ radeon->state.validated_bo_count = 0;
+}
+
+void radeon_validate_bo(radeonContextPtr radeon, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain)
+{
+ radeon_bo_ref(bo);
+ radeon->state.bos[radeon->state.validated_bo_count].bo = bo;
+ radeon->state.bos[radeon->state.validated_bo_count].read_domains = read_domains;
+ radeon->state.bos[radeon->state.validated_bo_count].write_domain = write_domain;
+ radeon->state.bos[radeon->state.validated_bo_count].new_accounted = 0;
+ radeon->state.validated_bo_count++;
+
+ assert(radeon->state.validated_bo_count < RADEON_MAX_BOS);
+}
+
void radeonEmitState(radeonContextPtr radeon)
{
if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw);
+ /* okay if we have no cmds in the buffer &&
+ we have no DMA flush &&
+ we have no DMA buffer allocated.
+ then no point flushing anything at all.
+ */
+ if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && !radeon->dma.current)
+ return;
+
if (radeon->dma.flush)
radeon->dma.flush( ctx );
}
radeon_cs_erase(rmesa->cmdbuf.cs);
rmesa->cmdbuf.flushing = 0;
+
+ if (radeon_revalidate_bos(rmesa->glCtx) == GL_FALSE) {
+ fprintf(stderr,"failed to revalidate buffers\n");
+ }
+
return ret;
}
radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]);
radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size);
} else {
- struct drm_radeon_gem_info mminfo;
+ struct drm_radeon_gem_info mminfo = { 0 };
if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
{
GL_CURRENT_BIT |
GL_DEPTH_BUFFER_BIT |
GL_ENABLE_BIT |
+ GL_POLYGON_BIT |
GL_STENCIL_BUFFER_BIT |
GL_TRANSFORM_BIT |
GL_CURRENT_BIT);
_mesa_Disable(GL_CLIP_PLANE3);
_mesa_Disable(GL_CLIP_PLANE4);
_mesa_Disable(GL_CLIP_PLANE5);
+ _mesa_PolygonMode(GL_FRONT_AND_BACK, GL_FILL);
if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) {
saved_fp_enable = GL_TRUE;
_mesa_Disable(GL_FRAGMENT_PROGRAM_ARB);
}
}
+#if FEATURE_ARB_vertex_buffer_object
+ _mesa_BindBufferARB(GL_ARRAY_BUFFER_ARB, 0);
+ _mesa_BindBufferARB(GL_ELEMENT_ARRAY_BUFFER_ARB, 0);
+#endif
+
radeon_meta_set_passthrough_transform(rmesa);
for (i = 0; i < 4; i++) {
projects / mesa.git / blobdiff