r300: set proper texture row alignment for IGP chips

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_common.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index a5b8d3253f864dde88873be6051cd94dcde14477..8b5b892f0df42c5ae46f8c5b548bb223d71d9677 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -789,14 +789,10 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
  */
 void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
 {
-       radeonContextPtr radeon = RADEON_CONTEXT(ctx);
-       
        if (RADEON_DEBUG & DEBUG_DRI)
                fprintf(stderr, "%s %s\n", __FUNCTION__,
                        _mesa_lookup_enum_by_nr( mode ));
        
-       radeon_firevertices(radeon);    /* don't pipeline cliprect changes */
-       
        radeon_draw_buffer(ctx, ctx->DrawBuffer);
 }
 
@@ -855,20 +851,57 @@ void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei he
        radeon_window_moved(radeon);
        radeon_draw_buffer(ctx, radeon->glCtx->DrawBuffer);
        ctx->Driver.Viewport = old_viewport;
-
-
 }
-static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state_atom *state )
-{
-       int i;
-       int dwords = (*state->check)(radeon->glCtx, state);
-
-       fprintf(stderr, "emit %s %d/%d\n", state->name, state->cmd_size, dwords);
 
-       if (RADEON_DEBUG & DEBUG_VERBOSE) 
-               for (i = 0 ; i < dwords; i++) 
-                       fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]);
+static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state_atom *state)
+{
+       int i, j, reg;
+       int dwords = (*state->check) (radeon->glCtx, state);
+       drm_r300_cmd_header_t cmd;
+
+       fprintf(stderr, "  emit %s %d/%d\n", state->name, dwords, state->cmd_size);
+
+       if (RADEON_DEBUG & DEBUG_VERBOSE) {
+               for (i = 0; i < dwords;) {
+                       cmd = *((drm_r300_cmd_header_t *) &state->cmd[i]);
+                       reg = (cmd.packet0.reghi << 8) | cmd.packet0.reglo;
+                       fprintf(stderr, "      %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n",
+                                       state->name, i, reg, cmd.packet0.count);
+                       ++i;
+                       for (j = 0; j < cmd.packet0.count && i < dwords; j++) {
+                               fprintf(stderr, "      %s[%d]: 0x%04x = %08x\n",
+                                               state->name, i, reg, state->cmd[i]);
+                               reg += 4;
+                               ++i;
+                       }
+               }
+       }
+}
 
+static void radeon_print_state_atom_kmm(radeonContextPtr radeon, struct radeon_state_atom *state)
+{
+       int i, j, reg, count;
+       int dwords = (*state->check) (radeon->glCtx, state);
+       uint32_t packet0;
+
+       fprintf(stderr, "  emit %s %d/%d\n", state->name, dwords, state->cmd_size);
+
+       if (RADEON_DEBUG & DEBUG_VERBOSE) {
+               for (i = 0; i < dwords;) {
+                       packet0 = state->cmd[i];
+                       reg = (packet0 & 0x1FFF) << 2;
+                       count = ((packet0 & 0x3FFF0000) >> 16) + 1;
+                       fprintf(stderr, "      %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n",
+                                       state->name, i, reg, count);
+                       ++i;
+                       for (j = 0; j < count && i < dwords; j++) {
+                               fprintf(stderr, "      %s[%d]: 0x%04x = %08x\n",
+                                               state->name, i, reg, state->cmd[i]);
+                               reg += 4;
+                               ++i;
+                       }
+               }
+       }
 }
 
 static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty)
@@ -886,7 +919,10 @@ static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty)
                        dwords = (*atom->check) (radeon->glCtx, atom);
                        if (dwords) {
                                if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
-                                       radeon_print_state_atom(radeon, atom);
+                                       if (radeon->radeonScreen->kernel_mm)
+                                               radeon_print_state_atom_kmm(radeon, atom);
+                                       else
+                                               radeon_print_state_atom(radeon, atom);
                                }
                                if (atom->emit) {
                                        (*atom->emit)(radeon->glCtx, atom);
@@ -932,6 +968,7 @@ void radeon_validate_reset_bos(radeonContextPtr radeon)
        int i;
 
        for (i = 0; i < radeon->state.validated_bo_count; i++) {
+               radeon_bo_unref(radeon->state.bos[i].bo);
                radeon->state.bos[i].bo = NULL;
                radeon->state.bos[i].read_domains = 0;
                radeon->state.bos[i].write_domain = 0;
@@ -942,6 +979,7 @@ void radeon_validate_reset_bos(radeonContextPtr radeon)
 
 void radeon_validate_bo(radeonContextPtr radeon, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain)
 {
+       radeon_bo_ref(bo);
        radeon->state.bos[radeon->state.validated_bo_count].bo = bo;
        radeon->state.bos[radeon->state.validated_bo_count].read_domains = read_domains;
        radeon->state.bos[radeon->state.validated_bo_count].write_domain = write_domain;
@@ -1148,7 +1186,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa)
                radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]);
                radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size);
        } else {
-               struct drm_radeon_gem_info mminfo;
+               struct drm_radeon_gem_info mminfo = { 0 };
 
                if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
                {
@@ -1260,6 +1298,7 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask)
                    GL_CURRENT_BIT |
                    GL_DEPTH_BUFFER_BIT |
                    GL_ENABLE_BIT |
+                   GL_POLYGON_BIT |
                    GL_STENCIL_BUFFER_BIT |
                    GL_TRANSFORM_BIT |
                    GL_CURRENT_BIT);
@@ -1281,6 +1320,7 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask)
    _mesa_Disable(GL_CLIP_PLANE3);
    _mesa_Disable(GL_CLIP_PLANE4);
    _mesa_Disable(GL_CLIP_PLANE5);
+   _mesa_PolygonMode(GL_FRONT_AND_BACK, GL_FILL);
    if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) {
       saved_fp_enable = GL_TRUE;
       _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB);
@@ -1313,6 +1353,11 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask)
       }
    }
   
+#if FEATURE_ARB_vertex_buffer_object
+   _mesa_BindBufferARB(GL_ARRAY_BUFFER_ARB, 0);
+   _mesa_BindBufferARB(GL_ELEMENT_ARRAY_BUFFER_ARB, 0);
+#endif
+
    radeon_meta_set_passthrough_transform(rmesa);
    
    for (i = 0; i < 4; i++) {