Merge branch 'mesa_7_6_branch' into mesa_7_7_branch

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_common.h

diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h
index c2fbb0950d5fd6a06e9955e5fe868ddbb7e86ec2..0608fe2418c5b7daa1804baa2678c37f4069956a 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common.h
@@ -5,18 +5,7 @@
 #include "radeon_dma.h"
 #include "radeon_texture.h"
 
-
-#define TRI_CLEAR_COLOR_BITS (BUFFER_BIT_BACK_LEFT |                   \
-                             BUFFER_BIT_FRONT_LEFT |                   \
-                             BUFFER_BIT_COLOR0 |                       \
-                             BUFFER_BIT_COLOR1 |                       \
-                             BUFFER_BIT_COLOR2 |                       \
-                             BUFFER_BIT_COLOR3 |                       \
-                             BUFFER_BIT_COLOR4 |                       \
-                             BUFFER_BIT_COLOR5 |                       \
-                             BUFFER_BIT_COLOR6 |                       \
-                             BUFFER_BIT_COLOR7)
-
+void radeonUserClear(GLcontext *ctx, GLuint mask);
 void radeonRecalcScissorRects(radeonContextPtr radeon);
 void radeonSetCliprects(radeonContextPtr radeon);
 void radeonUpdateScissor( GLcontext *ctx );
@@ -35,6 +24,7 @@ void radeonUpdatePageFlipping(radeonContextPtr rmesa);
 void radeonFlush(GLcontext *ctx);
 void radeonFinish(GLcontext * ctx);
 void radeonEmitState(radeonContextPtr radeon);
+GLuint radeonCountStateEmitSize(radeonContextPtr radeon);
 
 void radeon_clear_tris(GLcontext *ctx, GLbitfield mask);
 
@@ -47,16 +37,12 @@ void radeon_get_cliprects(radeonContextPtr radeon,
                          struct drm_clip_rect **cliprects,
                          unsigned int *num_cliprects,
                          int *x_off, int *y_off);
-GLboolean radeon_revalidate_bos(GLcontext *ctx);
-void radeon_validate_bo(radeonContextPtr radeon, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain);
-void radeon_validate_reset_bos(radeonContextPtr radeon);
-
 void radeon_fbo_init(struct radeon_context *radeon);
 void
 radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb,
                           struct radeon_bo *bo);
 struct radeon_renderbuffer *
-radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv);
+radeon_create_renderbuffer(gl_format format, __DRIdrawablePrivate *driDrawPriv);
 static inline struct radeon_renderbuffer *radeon_renderbuffer(struct gl_renderbuffer *rb)
 {
        struct radeon_renderbuffer *rrb = (struct radeon_renderbuffer *)rb;
@@ -77,7 +63,7 @@ static inline struct radeon_renderbuffer *radeon_get_renderbuffer(struct gl_fram
 static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa)
 {
        struct radeon_renderbuffer *rrb;
-       rrb = rmesa->state.depth.rrb;
+       rrb = radeon_renderbuffer(rmesa->state.depth.rb);
        if (!rrb)
                return NULL;
 
@@ -88,7 +74,7 @@ static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPt
 {
        struct radeon_renderbuffer *rrb;
 
-       rrb = rmesa->state.color.rrb;
+       rrb = radeon_renderbuffer(rmesa->state.color.rb);
        if (!rrb)
                return NULL;
        return rrb;