#include "swrast_setup/swrast_setup.h"
#include "tnl/tnl.h"
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
+#if defined(RADEON_R600)
#include "r600_context.h"
#endif
fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode");
radeon->iw.irq_seq = -1;
radeon->irqsEmitted = 0;
- if (IS_R600_CLASS(radeon->radeonScreen))
- radeon->do_irqs = 0;
- else
- radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
- radeon->radeonScreen->irq);
+ radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
+ radeon->radeonScreen->irq);
radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
else
radeon->texture_row_align = 32;
radeon->texture_rect_row_align = 64;
- radeon->texture_compressed_row_align = 64;
+ radeon->texture_compressed_row_align = 32;
}
- make_empty_list(&radeon->query.not_flushed_head);
radeon_init_dma(radeon);
return GL_TRUE;
static unsigned
radeon_bits_per_pixel(const struct radeon_renderbuffer *rb)
{
- switch (rb->base._ActualFormat) {
- case GL_RGB5:
- case GL_DEPTH_COMPONENT16:
- return 16;
- case GL_RGB8:
- case GL_RGBA8:
- case GL_DEPTH_COMPONENT24:
- case GL_DEPTH24_STENCIL8_EXT:
- case GL_STENCIL_INDEX8_EXT:
- return 32;
- default:
- return 0;
- }
+ return _mesa_get_format_bytes(rb->base.Format) * 8;
}
void