-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v 1.7 2003/02/08 21:26:45 dawes Exp $ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v 1.9 2003/09/24 02:43:12 dawes Exp $ */
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
#include "tnl/tnl.h"
#include "tnl/t_pipeline.h"
+#include "drivers/common/driverfuncs.h"
+
#include "radeon_context.h"
#include "radeon_ioctl.h"
#include "radeon_state.h"
#include "vblank.h"
#include "utils.h"
+#include "xmlpool.h" /* for symbolic values of enum-type options */
#ifndef RADEON_DEBUG
int RADEON_DEBUG = (0);
#endif
-
/* Return the width and height of the given buffer.
*/
static void radeonGetBufferSize( GLframebuffer *buffer,
offset = driGetRendererString( buffer, "Radeon", DRIVER_DATE,
agp_mode );
- sprintf( & buffer[ offset ], "%s %sTCL",
- ( rmesa->dri.drmMinor < 3 ) ? " DRM-COMPAT" : "",
+ sprintf( & buffer[ offset ], " %sTCL",
!(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
? "" : "NO-" );
"GL_EXT_blend_subtract",
"GL_EXT_secondary_color",
"GL_EXT_texture_edge_clamp",
- "GL_EXT_texture_env_add",
"GL_EXT_texture_env_combine",
"GL_EXT_texture_env_dot3",
"GL_EXT_texture_filter_anisotropic",
"GL_EXT_texture_lod_bias",
+ "GL_EXT_texture_mirror_clamp",
"GL_ATI_texture_env_combine3",
"GL_ATI_texture_mirror_once",
- "GL_IBM_texture_mirrored_repeat",
"GL_MESA_ycbcr_texture",
"GL_NV_blend_square",
"GL_SGIS_generate_mipmap",
- "GL_SGIS_texture_border_clamp",
- "GL_SGIS_texture_edge_clamp",
NULL
};
-extern const struct gl_pipeline_stage _radeon_texrect_stage;
-extern const struct gl_pipeline_stage _radeon_render_stage;
-extern const struct gl_pipeline_stage _radeon_tcl_stage;
+extern const struct tnl_pipeline_stage _radeon_texrect_stage;
+extern const struct tnl_pipeline_stage _radeon_render_stage;
+extern const struct tnl_pipeline_stage _radeon_tcl_stage;
-static const struct gl_pipeline_stage *radeon_pipeline[] = {
+static const struct tnl_pipeline_stage *radeon_pipeline[] = {
/* Try and go straight to t&l
*/
/* Initialize the driver's misc functions.
*/
-static void radeonInitDriverFuncs( GLcontext *ctx )
+static void radeonInitDriverFuncs( struct dd_function_table *functions )
{
- ctx->Driver.GetBufferSize = radeonGetBufferSize;
- ctx->Driver.ResizeBuffers = _swrast_alloc_buffers;
- ctx->Driver.GetString = radeonGetString;
-
- ctx->Driver.Error = NULL;
- ctx->Driver.DrawPixels = NULL;
- ctx->Driver.Bitmap = NULL;
+ functions->GetBufferSize = radeonGetBufferSize;
+ functions->ResizeBuffers = _swrast_alloc_buffers;
+ functions->GetString = radeonGetString;
}
static const struct dri_debug_control debug_control[] =
static int
-get_ust_nop( uint64_t * ust )
+get_ust_nop( int64_t * ust )
{
*ust = 1;
return 0;
{
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
+ struct dd_function_table functions;
radeonContextPtr rmesa;
GLcontext *ctx, *shareCtx;
int i;
+ int tcl_mode, fthrottle_mode;
assert(glVisual);
assert(driContextPriv);
if ( !rmesa )
return GL_FALSE;
+ /* Parse configuration files.
+ * Do this here so that initialMaxAnisotropy is set before we create
+ * the default textures.
+ */
+ driParseConfigFiles (&rmesa->optionCache, &screen->optionCache,
+ screen->driScreen->myNum, "radeon");
+ rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
+ "def_max_anisotropy");
+
+ /* Init default driver functions then plug in our Radeon-specific functions
+ * (the texture functions are especially important)
+ */
+ _mesa_init_driver_functions( &functions );
+ radeonInitDriverFuncs( &functions );
+ radeonInitTextureFuncs( &functions );
+
/* Allocate the Mesa context */
if (sharedContextPrivate)
shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx;
else
shareCtx = NULL;
- rmesa->glCtx = _mesa_create_context(glVisual, shareCtx, (void *) rmesa, GL_TRUE);
+ rmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
+ &functions, (void *) rmesa);
if (!rmesa->glCtx) {
FREE(rmesa);
return GL_FALSE;
rmesa->dri.hwContext = driContextPriv->hHWContext;
rmesa->dri.hwLock = &sPriv->pSAREA->lock;
rmesa->dri.fd = sPriv->fd;
-
- /* If we don't have 1.3, fallback to the 1.1 interfaces.
- */
- if (getenv("RADEON_COMPAT") || sPriv->drmMinor < 3 )
- rmesa->dri.drmMinor = 1;
- else
- rmesa->dri.drmMinor = sPriv->drmMinor;
+ rmesa->dri.drmMinor = sPriv->drmMinor;
rmesa->radeonScreen = screen;
- rmesa->sarea = (RADEONSAREAPrivPtr)((GLubyte *)sPriv->pSAREA +
+ rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
screen->sarea_priv_offset);
screen->texSize[i],
12,
RADEON_NR_TEX_REGIONS,
- rmesa->sarea->texList[i],
- & rmesa->sarea->texAge[i],
+ (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
+ & rmesa->sarea->tex_age[i],
& rmesa->swapped,
sizeof( radeonTexObj ),
(destroy_texture_object_t *) radeonDestroyTexObj );
driSetTextureSwapCounterLocation( rmesa->texture_heaps[i],
& rmesa->c_textureSwaps );
}
+ rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
+ "texture_depth");
+ if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
+ rmesa->texture_depth = ( screen->cpp == 4 ) ?
+ DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
rmesa->swtcl.RenderIndex = ~0;
rmesa->lost_context = 1;
ctx = rmesa->glCtx;
ctx->Const.MaxTextureUnits = 2;
+ ctx->Const.MaxTextureImageUnits = 2;
+ ctx->Const.MaxTextureCoordUnits = 2;
driCalculateMaxTextureLevels( rmesa->texture_heaps,
rmesa->nr_heaps,
MIN2( ctx->Const.MaxArrayLockSize,
RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
- rmesa->boxes = (getenv("LIBGL_PERFORMANCE_BOXES") != NULL);
+ rmesa->boxes = 0;
/* Initialize the software rasterizer and helper modules.
*/
_tnl_isolate_materials( ctx, GL_TRUE );
- /* Configure swrast to match hardware characteristics:
+ /* Configure swrast and T&L to match hardware characteristics:
*/
_swrast_allow_pixel_fog( ctx, GL_FALSE );
_swrast_allow_vertex_fog( ctx, GL_TRUE );
+ _tnl_allow_pixel_fog( ctx, GL_FALSE );
+ _tnl_allow_vertex_fog( ctx, GL_TRUE );
_math_matrix_ctr( &rmesa->TexGenMatrix[0] );
if (rmesa->dri.drmMinor >= 9)
_mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
- radeonInitDriverFuncs( ctx );
+ /* XXX these should really go right after _mesa_init_driver_functions() */
radeonInitIoctlFuncs( ctx );
radeonInitStateFuncs( ctx );
radeonInitSpanFuncs( ctx );
- radeonInitTextureFuncs( ctx );
radeonInitState( rmesa );
radeonInitSwtcl( ctx );
+ _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
+ ctx->Const.MaxArrayLockSize, 32 );
+
+ fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode");
rmesa->iw.irq_seq = -1;
rmesa->irqsEmitted = 0;
- rmesa->do_irqs = (rmesa->radeonScreen->irq && !getenv("RADEON_NO_IRQS"));
+ rmesa->do_irqs = (rmesa->radeonScreen->irq != 0 &&
+ fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
- rmesa->do_usleeps = !getenv("RADEON_NO_USLEEPS");
-
- rmesa->vblank_flags = (rmesa->do_irqs)
- ? driGetDefaultVBlankFlags() : VBLANK_FLAG_NO_IRQ;
+ rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
+ rmesa->vblank_flags = (rmesa->radeonScreen->irq != 0)
+ ? driGetDefaultVBlankFlags(&rmesa->optionCache) : VBLANK_FLAG_NO_IRQ;
#ifndef _SOLO
- rmesa->get_ust = (PFNGLXGETUSTPROC) glXGetProcAddress( "__glXGetUST" );
- if ( rmesa->get_ust == NULL )
-#endif
- {
+ rmesa->get_ust = (PFNGLXGETUSTPROC) glXGetProcAddress( (const GLubyte *) "__glXGetUST" );
+ if ( rmesa->get_ust == NULL ) {
rmesa->get_ust = get_ust_nop;
}
+#else
+ rmesa->get_ust = get_ust_nop;
+#endif
(*rmesa->get_ust)( & rmesa->swap_ust );
debug_control );
#endif
- if (getenv("RADEON_NO_RAST")) {
+ tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
+ if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D acceleration\n");
- FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
- }
- else if (getenv("RADEON_TCL_FORCE_ENABLE")) {
- fprintf(stderr, "Enabling TCL support... this will probably crash\n");
- fprintf(stderr, " your card if it isn't capable of TCL!\n");
- rmesa->radeonScreen->chipset |= RADEON_CHIPSET_TCL;
- } else if (getenv("RADEON_TCL_FORCE_DISABLE") ||
- rmesa->dri.drmMinor < 3 ||
- !(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
- rmesa->radeonScreen->chipset &= ~RADEON_CHIPSET_TCL;
- fprintf(stderr, "disabling TCL support\n");
- TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
+ FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
+ } else if (tcl_mode == DRI_CONF_TCL_SW ||
+ !(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
+ if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
+ rmesa->radeonScreen->chipset &= ~RADEON_CHIPSET_TCL;
+ fprintf(stderr, "Disabling HW TCL support\n");
+ }
+ TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
}
if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
- if (!getenv("RADEON_NO_VTXFMT"))
- radeonVtxfmtInit( ctx );
+ if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
+ radeonVtxfmtInit( ctx, tcl_mode >= DRI_CONF_TCL_CODEGEN );
_tnl_need_dlist_norm_lengths( ctx, GL_FALSE );
}
radeonFlushCmdBuf( rmesa, __FUNCTION__ );
}
- if (!rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
- if (!getenv("RADEON_NO_VTXFMT"))
+ if (!(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)) {
+ int tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
+ if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
radeonVtxfmtDestroy( rmesa->glCtx );
+ }
/* free the Mesa context */
rmesa->glCtx->DriverCtx = NULL;
_mesa_destroy_context( rmesa->glCtx );
+ _mesa_vector4f_free( &rmesa->tcl.ObjClean );
+
if (rmesa->state.scissor.pClipRects) {
FREE(rmesa->state.scissor.pClipRects);
rmesa->state.scissor.pClipRects = 0;
*/
int i;
- /* this assert is not correct, default textures are always on swap list
- assert( is_empty_list( & rmesa->swapped ) ); */
-
for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
driDestroyTextureHeap( rmesa->texture_heaps[ i ] );
rmesa->texture_heaps[ i ] = NULL;
}
+
+ assert( is_empty_list( & rmesa->swapped ) );
}
+ /* free the option cache */
+ driDestroyOptionCache (&rmesa->optionCache);
+
FREE( rmesa );
}
}
(radeonContextPtr) driContextPriv->driverPrivate;
if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx %p\n", __FUNCTION__, newCtx->glCtx);
+ fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx);
if ( newCtx->dri.drawable != driDrawPriv ) {
+ driDrawableInitVBlank( driDrawPriv, newCtx->vblank_flags );
newCtx->dri.drawable = driDrawPriv;
radeonUpdateWindow( newCtx->glCtx );
radeonUpdateViewportOffset( newCtx->glCtx );
}
-
+
_mesa_make_current2( newCtx->glCtx,
(GLframebuffer *) driDrawPriv->driverPrivate,
(GLframebuffer *) driReadPriv->driverPrivate );
radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx %p\n", __FUNCTION__, rmesa->glCtx);
+ fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->glCtx);
return GL_TRUE;
}
projects / mesa.git / blobdiff