fixup pci code for Jon's last checkin for changing page size

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_context.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index c68bab5f3420abd3a25b128fee7c35811fbaefb5..31ac5f253a3b16b895ef26369172924e3d0c3152 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -62,7 +62,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_vtxfmt.h"
 #include "radeon_maos.h"
 
-#define DRIVER_DATE    "20030328"
+#define DRIVER_DATE    "20041207"
 
 #include "vblank.h"
 #include "utils.h"
@@ -126,11 +126,13 @@ static const char * const card_extensions[] =
     "GL_ARB_texture_compression",
     "GL_ARB_texture_env_add",
     "GL_ARB_texture_env_combine",
+    "GL_ARB_texture_env_crossbar",
     "GL_ARB_texture_env_dot3",
     "GL_ARB_texture_mirrored_repeat",
     "GL_EXT_blend_logic_op",
     "GL_EXT_blend_subtract",
     "GL_EXT_secondary_color",
+    "GL_EXT_stencil_wrap",
     "GL_EXT_texture_edge_clamp",
     "GL_EXT_texture_env_combine",
     "GL_EXT_texture_env_dot3",
@@ -244,6 +246,14 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
                                                  "def_max_anisotropy");
 
+   if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
+      if ( sPriv->drmMinor < 13 )
+        fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
+                         "disabling.\n",sPriv->drmMinor );
+      else
+        rmesa->using_hyperz = GL_TRUE;
+   }
+
    /* Init default driver functions then plug in our Radeon-specific functions
     * (the texture functions are especially important)
     */
@@ -274,7 +284,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    rmesa->dri.drmMinor = sPriv->drmMinor;
 
    rmesa->radeonScreen = screen;
-   rmesa->sarea = (RADEONSAREAPrivPtr)((GLubyte *)sPriv->pSAREA +
+   rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
                                       screen->sarea_priv_offset);
 
 
@@ -289,8 +299,8 @@ radeonCreateContext( const __GLcontextModes *glVisual,
            screen->texSize[i],
            12,
            RADEON_NR_TEX_REGIONS,
-           rmesa->sarea->texList[i],
-           & rmesa->sarea->texAge[i],
+           (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
+           & rmesa->sarea->tex_age[i],
            & rmesa->swapped,
            sizeof( radeonTexObj ),
            (destroy_texture_object_t *) radeonDestroyTexObj );
@@ -305,7 +315,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
         DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 
    rmesa->swtcl.RenderIndex = ~0;
-   rmesa->lost_context = 1;
+   rmesa->hw.all_dirty = GL_TRUE;
 
    /* Set the maximum texture size small enough that we can guarentee that
     * all texture units can bind a maximal texture and have them both in
@@ -396,6 +406,13 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    _math_matrix_set_identity( &rmesa->tmpmat );
 
    driInitExtensions( ctx, card_extensions, GL_TRUE );
+   if (rmesa->glCtx->Mesa_DXTn) {
+      _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
+      _mesa_enable_extension( ctx, "GL_S3_s3tc" );
+   }
+   else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) {
+      _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
+   }
 
    if (rmesa->dri.drmMinor >= 9)
       _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
@@ -420,15 +437,11 @@ radeonCreateContext( const __GLcontextModes *glVisual,
 
    rmesa->vblank_flags = (rmesa->radeonScreen->irq != 0)
        ? driGetDefaultVBlankFlags(&rmesa->optionCache) : VBLANK_FLAG_NO_IRQ;
-#ifndef _SOLO
+
    rmesa->get_ust = (PFNGLXGETUSTPROC) glXGetProcAddress( (const GLubyte *) "__glXGetUST" );
    if ( rmesa->get_ust == NULL ) {
       rmesa->get_ust = get_ust_nop;
    }
-#else
-   rmesa->get_ust = get_ust_nop;
-#endif   
-
    (*rmesa->get_ust)( & rmesa->swap_ust );
 
 
@@ -440,12 +453,14 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
    if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
       fprintf(stderr, "disabling 3D acceleration\n");
-      FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1); 
+      FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
    } else if (tcl_mode == DRI_CONF_TCL_SW ||
              !(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
-      rmesa->radeonScreen->chipset &= ~RADEON_CHIPSET_TCL;
-      fprintf(stderr, "disabling TCL support\n");
-      TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1); 
+      if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
+        rmesa->radeonScreen->chipset &= ~RADEON_CHIPSET_TCL;
+        fprintf(stderr, "Disabling HW TCL support\n");
+      }
+      TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
    }
 
    if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
@@ -587,11 +602,6 @@ radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
                           (GLframebuffer *) driDrawPriv->driverPrivate,
                           (GLframebuffer *) driReadPriv->driverPrivate );
 
-      if ( !newCtx->glCtx->Viewport.Width ) {
-        _mesa_set_viewport( newCtx->glCtx, 0, 0,
-                            driDrawPriv->w, driDrawPriv->h );
-      }
-
       if (newCtx->vb.enabled)
         radeonVtxfmtMakeCurrent( newCtx->glCtx );