mesa: add bool param to _mesa_free_context_data

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_context.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index db1cc7274dbde313b56ba5a774538a49215570d1..5a1c01fdd0df751e899601d7e4aff85521399e96 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -40,7 +40,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "main/api_exec.h"
 #include "main/context.h"
 #include "util/simple_list.h"
-#include "main/imports.h"
 #include "main/extensions.h"
 #include "main/version.h"
 #include "main/vtxfmt.h"
@@ -67,7 +66,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_fog.h"
 
 #include "utils.h"
-#include "util/xmlpool.h" /* for symbolic values of enum-type options */
+#include "util/driconf.h" /* for symbolic values of enum-type options */
 
 extern const struct tnl_pipeline_stage _radeon_render_stage;
 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
@@ -76,7 +75,7 @@ static const struct tnl_pipeline_stage *radeon_pipeline[] = {
 
    /* Try and go straight to t&l
     */
-   &_radeon_tcl_stage,  
+   &_radeon_tcl_stage,
 
    /* Catch any t&l fallbacks
     */
@@ -95,7 +94,7 @@ static const struct tnl_pipeline_stage *radeon_pipeline[] = {
 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 {
    r100ContextPtr rmesa = (r100ContextPtr)radeon;
-   
+
    /* r100 always needs to emit ZBS to avoid TCL lockups */
    rmesa->hw.zbs.dirty = 1;
    radeon->hw.is_dirty = 1;
@@ -114,7 +113,7 @@ static void r100_emit_query_finish(radeonContextPtr radeon)
 
    BEGIN_BATCH(4);
    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
-   OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
+   OUT_BATCH_RELOC(query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
    END_BATCH();
    query->curr_offset += sizeof(uint32_t);
    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
@@ -177,13 +176,13 @@ r100CreateContext( gl_api api,
 
    /* init exp fog table data */
    radeonInitStaticFogData();
-   
+
    /* Parse configuration files.
     * Do this here so that initialMaxAnisotropy is set before we create
     * the default textures.
     */
    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
-                       screen->driScreen->myNum, "radeon", NULL);
+                       screen->driScreen->myNum, "radeon", NULL, NULL, 0);
    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
                                                  "def_max_anisotropy");
 
@@ -216,10 +215,9 @@ r100CreateContext( gl_api api,
    /* Initialize the software rasterizer and helper modules.
     */
    _swrast_CreateContext( ctx );
-   _vbo_CreateContext( ctx );
+   _vbo_CreateContext( ctx, false );
    _tnl_CreateContext( ctx );
    _swsetup_CreateContext( ctx );
-   _ae_create_context( ctx );
 
    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
                                                 "texture_units");
@@ -229,9 +227,9 @@ r100CreateContext( gl_api api,
 
    ctx->Const.StripTextureBorder = GL_TRUE;
 
-   /* FIXME: When no memory manager is available we should set this 
+   /* FIXME: When no memory manager is available we should set this
     * to some reasonable value based on texture memory pool size */
-   ctx->Const.MaxTextureLevels = 12;
+   ctx->Const.MaxTextureSize = 2048;
    ctx->Const.Max3DTextureLevels = 9;
    ctx->Const.MaxCubeTextureLevels = 12;
    ctx->Const.MaxTextureRectSize = 2048;
@@ -256,9 +254,9 @@ r100CreateContext( gl_api api,
     * fit in a single dma buffer for indexed rendering of quad strips,
     * etc.
     */
-   ctx->Const.MaxArrayLockSize = 
-      MIN2( ctx->Const.MaxArrayLockSize, 
-           RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE ); 
+   ctx->Const.MaxArrayLockSize =
+      MIN2( ctx->Const.MaxArrayLockSize,
+           RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 
    rmesa->boxes = 0;
 
@@ -320,7 +318,7 @@ r100CreateContext( gl_api api,
    radeonInitState( rmesa );
    radeonInitSwtcl( ctx );
 
-   _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0, 
+   _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
                         ctx->Const.MaxArrayLockSize, 32 );
 
    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");