radeon: fix up span function setting
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_context.h
index 75ec2d15dd8f0b87520b78fde30d0e278e03e295..2015e96a743f545b5d9acdfe0c17838a76eee011 100644 (file)
@@ -48,32 +48,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "drm.h"
 #include "radeon_drm.h"
 #include "texmem.h"
-
 #include "main/macros.h"
 #include "main/mtypes.h"
 #include "main/colormac.h"
-
-struct radeon_context;
-typedef struct radeon_context radeonContextRec;
-typedef struct radeon_context *radeonContextPtr;
-
-#include "radeon_lock.h"
 #include "radeon_screen.h"
 
-#include "common_context.h"
+#include "radeon_common.h"
 
-#define R100_TEX_ALL 0x7
 
-typedef void (*radeon_tri_func) (radeonContextPtr,
-                                radeonVertex *,
-                                radeonVertex *, radeonVertex *);
+struct r100_context;
+typedef struct r100_context r100ContextRec;
+typedef struct r100_context *r100ContextPtr;
 
-typedef void (*radeon_line_func) (radeonContextPtr,
-                                 radeonVertex *, radeonVertex *);
+#include "radeon_lock.h"
 
-typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 
 
+#define R100_TEX_ALL 0x7
 
 /* used for both tcl_vtx and vc_frmt tex bits (they are identical) */
 #define RADEON_ST_BIT(unit) \
@@ -304,10 +295,7 @@ struct radeon_texture_state {
 #define SHN_SHININESS      1
 #define SHN_STATE_SIZE     2
 
-struct radeon_hw_state {
-       /* Head of the linked list of state atoms. */
-       struct radeon_state_atom atomlist;
-
+struct r100_hw_state {
        /* Hardware state, stored as cmdbuf commands:  
         *   -- Need to doublebuffer for
         *           - eliding noop statechange loops? (except line stipple count)
@@ -332,55 +320,16 @@ struct radeon_hw_state {
        struct radeon_state_atom glt;
        struct radeon_state_atom txr[3];        /* for NPOT */
 
-       int max_state_size;     /* Number of bytes necessary for a full state emit. */
-       GLboolean is_dirty, all_dirty;
 };
 
-struct radeon_state {
-       /* Derived state for internal purposes:
-        */
-       struct radeon_colorbuffer_state color;
-       struct radeon_depthbuffer_state depth;
-       struct radeon_scissor_state scissor;
-       struct radeon_stencilbuffer_state stencil;
+
+struct r100_state {
        struct radeon_stipple_state stipple;
        struct radeon_texture_state texture;
 };
 
-#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset +                      \
-                       (rvb)->address - rmesa->dma.buf0_address +      \
-                       (rvb)->start)
-
-struct radeon_dri_mirror {
-       __DRIcontextPrivate *context;   /* DRI context */
-       __DRIscreenPrivate *screen;     /* DRI screen */
-
-   /**
-    * DRI drawable bound to this context for drawing.
-    */
-       __DRIdrawablePrivate *drawable;
-
-   /**
-    * DRI drawable bound to this context for reading.
-    */
-       __DRIdrawablePrivate *readable;
-
-       drm_context_t hwContext;
-       drm_hw_lock_t *hwLock;
-       int fd;
-       int drmMinor;
-};
-
 #define RADEON_CMD_BUF_SZ  (8*1024)
-
-struct radeon_store {
-       GLuint statenr;
-       GLuint primnr;
-       char cmd_buf[RADEON_CMD_BUF_SZ];
-       int cmd_used;
-       int elts_start;
-};
-
+#define R200_ELT_BUF_SZ  (8*1024)
 /* radeon_tcl.c
  */
 struct radeon_tcl_info {
@@ -392,30 +341,23 @@ struct radeon_tcl_info {
         */
        GLvector4f ObjClean;
 
-       struct radeon_dma_region *aos_components[8];
+        struct radeon_aos aos[8];
        GLuint nr_aos_components;
 
        GLuint *Elts;
 
-       struct radeon_dma_region indexed_verts;
-       struct radeon_dma_region obj;
-       struct radeon_dma_region rgba;
-       struct radeon_dma_region spec;
-       struct radeon_dma_region fog;
-       struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS];
-       struct radeon_dma_region norm;
+       struct radeon_bo *indexed_bo;
+
+        int elt_cmd_offset; /** Offset into the cmdbuf */
+       int elt_cmd_start;
+        int elt_used;
 };
 
 /* radeon_swtcl.c
  */
-struct radeon_swtcl_info {
-       GLuint RenderIndex;
-       GLuint vertex_size;
+struct r100_swtcl_info {
        GLuint vertex_format;
 
-       struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
-       GLuint vertex_attr_count;
-
        GLubyte *verts;
 
        /* Fallback rasterization functions
@@ -424,10 +366,6 @@ struct radeon_swtcl_info {
        radeon_line_func draw_line;
        radeon_tri_func draw_tri;
 
-       GLuint hw_primitive;
-       GLenum render_primitive;
-       GLuint numverts;
-
    /**
     * Offset of the 4UB color data within a hardware (swtcl) vertex.
     */
@@ -439,8 +377,6 @@ struct radeon_swtcl_info {
        GLuint specoffset;
 
        GLboolean needproj;
-
-       struct radeon_dma_region indexed_verts;
 };
 
 
@@ -454,59 +390,18 @@ struct radeon_swtcl_info {
  */
 #define RADEON_MAX_VERTEX_SIZE 20
 
-struct radeon_context {
-       GLcontext *glCtx;       /* Mesa context */
+struct r100_context {
+        struct radeon_context radeon;
 
        /* Driver and hardware state management
         */
-       struct radeon_hw_state hw;
-       struct radeon_state state;
-
-       /* Texture object bookkeeping
-        */
-       unsigned nr_heaps;
-       driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
-       driTextureObject swapped;
-       int texture_depth;
-       float initialMaxAnisotropy;
-
-       /* Rasterization and vertex state:
-        */
-       GLuint TclFallback;
-       GLuint Fallback;
-       GLuint NewGLState;
-        DECLARE_RENDERINPUTS(tnl_index_bitset);        /* index of bits for last tnl_install_attrs */
+       struct r100_hw_state hw;
+       struct r100_state state;
 
        /* Vertex buffers
         */
        struct radeon_ioctl ioctl;
-       struct radeon_dma dma;
        struct radeon_store store;
-       /* A full state emit as of the first state emit in the main store, in case
-        * the context is lost.
-        */
-       struct radeon_store backup_store;
-
-       /* Page flipping
-        */
-       GLuint doPageFlip;
-
-       /* Busy waiting
-        */
-       GLuint do_usleeps;
-       GLuint do_irqs;
-       GLuint irqsEmitted;
-       drm_radeon_irq_wait_t iw;
-
-       /* Drawable, cliprect and scissor information
-        */
-       GLuint numClipRects;    /* Cliprects for the draw buffer */
-       drm_clip_rect_t *pClipRects;
-       unsigned int lastStamp;
-       GLboolean lost_context;
-       GLboolean save_on_next_emit;
-       radeonScreenPtr radeonScreen;   /* Screen private DRI data */
-       drm_radeon_sarea_t *sarea;      /* Private SAREA data */
 
        /* TCL stuff
         */
@@ -519,29 +414,13 @@ struct radeon_context {
        GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS];
        GLuint last_ReallyEnabled;
 
-       /* VBI
-        */
-       int64_t swap_ust;
-       int64_t swap_missed_ust;
-
-       GLuint swap_count;
-       GLuint swap_missed_count;
-
        /* radeon_tcl.c
         */
        struct radeon_tcl_info tcl;
 
        /* radeon_swtcl.c
         */
-       struct radeon_swtcl_info swtcl;
-
-       /* Mirrors of some DRI state
-        */
-       struct radeon_dri_mirror dri;
-
-       /* Configuration cache
-        */
-       driOptionCache optionCache;
+       struct r100_swtcl_info swtcl;
 
        GLboolean using_hyperz;
        GLboolean texmicrotile;
@@ -555,9 +434,25 @@ struct radeon_context {
        GLuint c_textureSwaps;
        GLuint c_textureBytes;
        GLuint c_vertexBuffers;
+
+  struct {
+      struct gl_fragment_program *bitmap_fp;
+      struct gl_vertex_program *passthrough_vp;
+
+      struct gl_fragment_program *saved_fp;
+      GLboolean saved_fp_enable;
+      struct gl_vertex_program *saved_vp;
+      GLboolean saved_vp_enable;
+
+      GLint saved_vp_x, saved_vp_y;
+      GLsizei saved_vp_width, saved_vp_height;
+      GLenum saved_matrix_mode;
+   } meta;
+
 };
 
-#define RADEON_CONTEXT(ctx)            ((radeonContextPtr)(ctx->DriverCtx))
+
+#define R100_CONTEXT(ctx)              ((r100ContextPtr)(ctx->DriverCtx))
 
 
 #define RADEON_OLD_PACKETS 1
@@ -566,37 +461,11 @@ extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
 extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
                                     __DRIcontextPrivate * driContextPriv,
                                     void *sharedContextPrivate);
-extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv);
-extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
-                               int x, int y, int w, int h);
 extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
                                   __DRIdrawablePrivate * driDrawPriv,
                                   __DRIdrawablePrivate * driReadPriv);
 extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
 
-/* ================================================================
- * Debugging:
- */
-#define DO_DEBUG               1
-
-#if DO_DEBUG
-extern int RADEON_DEBUG;
-#else
-#define RADEON_DEBUG           0
-#endif
-
-#define DEBUG_TEXTURE  0x0001
-#define DEBUG_STATE    0x0002
-#define DEBUG_IOCTL    0x0004
-#define DEBUG_PRIMS    0x0008
-#define DEBUG_VERTS    0x0010
-#define DEBUG_FALLBACKS        0x0020
-#define DEBUG_VFMT     0x0040
-#define DEBUG_CODEGEN  0x0080
-#define DEBUG_VERBOSE  0x0100
-#define DEBUG_DRI       0x0200
-#define DEBUG_DMA       0x0400
-#define DEBUG_SANITY    0x0800
-#define DEBUG_SYNC      0x1000
+
 
 #endif                         /* __RADEON_CONTEXT_H__ */