#ifndef __RADEON_CONTEXT_H__
#define __RADEON_CONTEXT_H__
-#ifdef GLX_DIRECT_RENDERING
-
-#include <inttypes.h>
+#include "tnl/t_vertex.h"
#include "dri_util.h"
-#include "radeon_common.h"
+#include "drm.h"
+#include "radeon_drm.h"
#include "texmem.h"
#include "macros.h"
#include "radeon_screen.h"
#include "mm.h"
+#include "math/m_vector.h"
+
/* Flags for software fallback cases */
/* See correponding strings in radeon_swtcl.c */
#define RADEON_FALLBACK_TEXTURE 0x0001
struct radeon_colorbuffer_state {
GLuint clear;
GLint drawOffset, drawPitch;
+ int roundEnable;
};
};
struct radeon_scissor_state {
- XF86DRIClipRectRec rect;
+ drm_clip_rect_t rect;
GLboolean enabled;
GLuint numClipRects; /* Cliprects active */
GLuint numAllocedClipRects; /* Cliprects available */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
};
struct radeon_stencilbuffer_state {
brought into the
texunit. */
- drmRadeonTexImage image[6][RADEON_MAX_TEXTURE_LEVELS];
+ drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
/* Six, for the cube faces */
GLuint pp_txfilter; /* hardware register values */
GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */
GLboolean border_fallback;
+
+ GLuint tile_bits; /* hw texture tile bits used on this texture */
};
GLuint is_tcl;
int *cmd; /* one or more cmd's */
int *lastcmd; /* one or more cmd's */
+ GLboolean dirty; /* dirty-mark in emit_state_list */
GLboolean (*check)( GLcontext * ); /* is this state active? */
};
-
+
/* Trying to keep these relatively short as the variables are becoming
#define LIT_DIRECTION_Y 18
#define LIT_DIRECTION_Z 19
#define LIT_DIRECTION_W 20
-#define LIT_ATTEN_CONST 21
+#define LIT_ATTEN_QUADRATIC 21
#define LIT_ATTEN_LINEAR 22
-#define LIT_ATTEN_QUADRATIC 23
+#define LIT_ATTEN_CONST 23
#define LIT_ATTEN_XXX 24
#define LIT_CMD_1 25
#define LIT_SPOT_DCD 26
#define LIT_SPOT_CUTOFF 28
#define LIT_SPECULAR_THRESH 29
#define LIT_RANGE_CUTOFF 30 /* ? */
-#define LIT_RANGE_ATTEN 31 /* ? */
+#define LIT_ATTEN_CONST_INV 31
#define LIT_STATE_SIZE 32
/* Fog
struct radeon_hw_state {
- /* All state should be on one of these lists:
- */
- struct radeon_state_atom dirty; /* dirty list head placeholder */
- struct radeon_state_atom clean; /* clean list head placeholder */
+ /* Head of the linked list of state atoms. */
+ struct radeon_state_atom atomlist;
/* Hardware state, stored as cmdbuf commands:
* -- Need to doublebuffer for
- * - reviving state after loss of context
* - eliding noop statechange loops? (except line stipple count)
*/
struct radeon_state_atom ctx;
struct radeon_state_atom fog;
struct radeon_state_atom glt;
struct radeon_state_atom txr[2]; /* for NPOT */
+
+ int max_state_size; /* Number of bytes necessary for a full state emit. */
+ GLboolean is_dirty, all_dirty;
};
struct radeon_state {
drmBufPtr buf;
};
-#define GET_START(rvb) (rmesa->radeonScreen->agp_buffer_offset + \
+#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \
(rvb)->address - rmesa->dma.buf0_address + \
(rvb)->start)
__DRIscreenPrivate *screen; /* DRI screen */
__DRIdrawablePrivate *drawable; /* DRI drawable bound to this ctx */
- drmContext hwContext;
- drmLock *hwLock;
+ drm_context_t hwContext;
+ drm_hw_lock_t *hwLock;
int fd;
int drmMinor;
};
GLint last_offset;
GLuint hw_primitive;
+ /* Temporary for cases where incoming vertex data is incompatible
+ * with maos code.
+ */
+ GLvector4f ObjClean;
+
struct radeon_dma_region *aos_components[8];
GLuint nr_aos_components;
/* radeon_swtcl.c
*/
struct radeon_swtcl_info {
- GLuint SetupIndex;
- GLuint SetupNewInputs;
GLuint RenderIndex;
GLuint vertex_size;
- GLuint vertex_stride_shift;
GLuint vertex_format;
+
+ struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
+ GLuint vertex_attr_count;
+
GLubyte *verts;
/* Fallback rasterization functions
GLenum render_primitive;
GLuint numverts;
+ /**
+ * Offset of the 4UB color data within a hardware (swtcl) vertex.
+ */
+ GLuint coloroffset;
+
+ /**
+ * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
+ */
+ GLuint specoffset;
+
+ GLboolean needproj;
+
struct radeon_dma_region indexed_verts;
};
unsigned nr_heaps;
driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ];
driTextureObject swapped;
-
+ int texture_depth;
+ float initialMaxAnisotropy;
/* Rasterization and vertex state:
*/
GLuint TclFallback;
GLuint Fallback;
GLuint NewGLState;
-
-
- /* Temporaries for translating away float colors:
- */
- struct gl_client_array UbyteColor;
- struct gl_client_array UbyteSecondaryColor;
+ GLuint tnl_index; /* index of bits for last tnl_install_attrs */
/* Vertex buffers
*/
struct radeon_ioctl ioctl;
struct radeon_dma dma;
struct radeon_store store;
+ /* A full state emit as of the first state emit in the main store, in case
+ * the context is lost.
+ */
+ struct radeon_store backup_store;
/* Page flipping
*/
GLuint do_usleeps;
GLuint do_irqs;
GLuint irqsEmitted;
- drmRadeonIrqWait iw;
+ drm_radeon_irq_wait_t iw;
/* Drawable, cliprect and scissor information
*/
GLuint numClipRects; /* Cliprects for the draw buffer */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
unsigned int lastStamp;
GLboolean lost_context;
+ GLboolean save_on_next_emit;
radeonScreenPtr radeonScreen; /* Screen private DRI data */
- RADEONSAREAPrivPtr sarea; /* Private SAREA data */
+ drm_radeon_sarea_t *sarea; /* Private SAREA data */
/* TCL stuff
*/
GLuint vbl_seq;
GLuint vblank_flags;
- uint64_t swap_ust;
- uint64_t swap_missed_ust;
+ int64_t swap_ust;
+ int64_t swap_missed_ust;
GLuint swap_count;
GLuint swap_missed_count;
*/
struct radeon_dri_mirror dri;
-
+ /* Configuration cache
+ */
+ driOptionCache optionCache;
+
+ GLboolean using_hyperz;
+ GLboolean texmicrotile;
+
/* Performance counters
*/
GLuint boxes; /* Draw performance boxes */
#define DEBUG_DRI 0x200
#define DEBUG_DMA 0x400
#define DEBUG_SANITY 0x800
+#define DEBUG_SYNC 0x1000
-#endif
#endif /* __RADEON_CONTEXT_H__ */
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