Remove all the radeon_subset files. They were completely unused. Keith

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_context.h

diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h
index 64373e1b1706a397d4a14a56376125d8c51c7f80..8d0637ca326f0beba11ad0640451f19fe556f588 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -38,11 +38,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #ifndef __RADEON_CONTEXT_H__
 #define __RADEON_CONTEXT_H__
 
-#ifdef GLX_DIRECT_RENDERING
-
-#include <inttypes.h>
 #include "dri_util.h"
-#include "radeon_common.h"
+#include "drm.h"
+#include "radeon_drm.h"
 #include "texmem.h"
 
 #include "macros.h"
@@ -111,12 +109,12 @@ struct radeon_pixel_state {
 };
 
 struct radeon_scissor_state {
-   XF86DRIClipRectRec rect;
+   drm_clip_rect_t rect;
    GLboolean enabled;
 
    GLuint numClipRects;                        /* Cliprects active */
    GLuint numAllocedClipRects;         /* Cliprects available */
-   XF86DRIClipRectPtr pClipRects;
+   drm_clip_rect_t *pClipRects;
 };
 
 struct radeon_stencilbuffer_state {
@@ -151,7 +149,7 @@ struct radeon_tex_obj {
                                           brought into the
                                           texunit. */
 
-   drmRadeonTexImage image[6][RADEON_MAX_TEXTURE_LEVELS];
+   drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
                                        /* Six, for the cube faces */
 
    GLuint pp_txfilter;                 /* hardware register values */
@@ -164,6 +162,8 @@ struct radeon_tex_obj {
    GLuint pp_cubic_faces;              /* cube face 1,2,3,4 log2 sizes */
 
    GLboolean  border_fallback;
+
+   GLuint tile_bits;                   /* hw texture tile bits used on this texture */
 };
 
 
@@ -185,9 +185,10 @@ struct radeon_state_atom {
    GLuint is_tcl;
    int *cmd;                            /* one or more cmd's */
    int *lastcmd;                        /* one or more cmd's */
+   GLboolean dirty;                      /* dirty-mark in emit_state_list */
    GLboolean (*check)( GLcontext * );    /* is this state active? */
 };
-   
+
 
 
 /* Trying to keep these relatively short as the variables are becoming
@@ -339,9 +340,9 @@ struct radeon_state_atom {
 #define LIT_DIRECTION_Y            18
 #define LIT_DIRECTION_Z            19
 #define LIT_DIRECTION_W            20
-#define LIT_ATTEN_CONST            21
+#define LIT_ATTEN_QUADRATIC        21
 #define LIT_ATTEN_LINEAR           22
-#define LIT_ATTEN_QUADRATIC        23
+#define LIT_ATTEN_CONST            23
 #define LIT_ATTEN_XXX              24
 #define LIT_CMD_1                  25
 #define LIT_SPOT_DCD               26
@@ -349,7 +350,7 @@ struct radeon_state_atom {
 #define LIT_SPOT_CUTOFF            28
 #define LIT_SPECULAR_THRESH        29
 #define LIT_RANGE_CUTOFF           30 /* ? */
-#define LIT_RANGE_ATTEN            31 /* ? */
+#define LIT_ATTEN_CONST_INV        31
 #define LIT_STATE_SIZE             32
 
 /* Fog
@@ -397,14 +398,11 @@ struct radeon_state_atom {
 
 
 struct radeon_hw_state {
-   /* All state should be on one of these lists:
-    */
-   struct radeon_state_atom dirty; /* dirty list head placeholder */
-   struct radeon_state_atom clean; /* clean list head placeholder */
+   /* Head of the linked list of state atoms. */
+   struct radeon_state_atom atomlist;
 
    /* Hardware state, stored as cmdbuf commands:  
     *   -- Need to doublebuffer for
-    *           - reviving state after loss of context
     *           - eliding noop statechange loops? (except line stipple count)
     */
    struct radeon_state_atom ctx;
@@ -425,6 +423,9 @@ struct radeon_hw_state {
    struct radeon_state_atom fog; 
    struct radeon_state_atom glt; 
    struct radeon_state_atom txr[2]; /* for NPOT */
+
+   int max_state_size; /* Number of bytes necessary for a full state emit. */
+   GLboolean is_dirty, all_dirty;
 };
 
 struct radeon_state {
@@ -481,8 +482,8 @@ struct radeon_dri_mirror {
    __DRIscreenPrivate  *screen;        /* DRI screen */
    __DRIdrawablePrivate        *drawable;      /* DRI drawable bound to this ctx */
 
-   drmContext hwContext;
-   drmLock *hwLock;
+   drm_context_t hwContext;
+   drm_hw_lock_t *hwLock;
    int fd;
    int drmMinor;
 };
@@ -699,7 +700,7 @@ struct radeon_context {
    driTexHeap          * texture_heaps[ RADEON_NR_TEX_HEAPS ];
    driTextureObject      swapped;
    int                   texture_depth;
-
+   float                 initialMaxAnisotropy;
 
    /* Rasterization and vertex state:
     */
@@ -712,6 +713,10 @@ struct radeon_context {
    struct radeon_ioctl ioctl;
    struct radeon_dma dma;
    struct radeon_store store;
+   /* A full state emit as of the first state emit in the main store, in case
+    * the context is lost.
+    */
+   struct radeon_store backup_store;
 
    /* Page flipping
     */
@@ -722,16 +727,17 @@ struct radeon_context {
    GLuint do_usleeps;
    GLuint do_irqs;
    GLuint irqsEmitted;
-   drmRadeonIrqWait iw;
+   drm_radeon_irq_wait_t iw;
 
    /* Drawable, cliprect and scissor information
     */
    GLuint numClipRects;                        /* Cliprects for the draw buffer */
-   XF86DRIClipRectPtr pClipRects;
+   drm_clip_rect_t *pClipRects;
    unsigned int lastStamp;
    GLboolean lost_context;
+   GLboolean save_on_next_emit;
    radeonScreenPtr radeonScreen;       /* Screen private DRI data */
-   RADEONSAREAPrivPtr sarea;           /* Private SAREA data */
+   drm_radeon_sarea_t *sarea;          /* Private SAREA data */
 
    /* TCL stuff
     */
@@ -748,8 +754,8 @@ struct radeon_context {
    GLuint vbl_seq;
    GLuint vblank_flags;
 
-   uint64_t swap_ust;
-   uint64_t swap_missed_ust;
+   int64_t swap_ust;
+   int64_t swap_missed_ust;
 
    GLuint swap_count;
    GLuint swap_missed_count;
@@ -776,7 +782,9 @@ struct radeon_context {
     */
    driOptionCache optionCache;
 
- 
+   GLboolean using_hyperz;
+   GLboolean texmicrotile;
+
    /* Performance counters
     */
    GLuint boxes;                       /* Draw performance boxes */
@@ -841,6 +849,6 @@ extern int RADEON_DEBUG;
 #define DEBUG_DRI       0x200
 #define DEBUG_DMA       0x400
 #define DEBUG_SANITY    0x800
+#define DEBUG_SYNC     0x1000
 
-#endif
 #endif /* __RADEON_CONTEXT_H__ */