#include "drm.h"
#include "radeon_drm.h"
#include "texmem.h"
-
#include "main/macros.h"
#include "main/mtypes.h"
#include "main/colormac.h"
-
-struct radeon_context;
-typedef struct radeon_context radeonContextRec;
-typedef struct radeon_context *radeonContextPtr;
-
-/* This union is used to avoid warnings/miscompilation
- with float to uint32_t casts due to strict-aliasing */
-typedef union {
- GLfloat f;
- uint32_t ui32;
-} float_ui32_type;
-
-#include "radeon_lock.h"
#include "radeon_screen.h"
-#include "main/mm.h"
-
-#include "math/m_vector.h"
-
-#define TEX_0 0x1
-#define TEX_1 0x2
-#define TEX_2 0x4
-#define TEX_ALL 0x7
-
-/* Rasterizing fallbacks */
-/* See correponding strings in r200_swtcl.c */
-#define RADEON_FALLBACK_TEXTURE 0x0001
-#define RADEON_FALLBACK_DRAW_BUFFER 0x0002
-#define RADEON_FALLBACK_STENCIL 0x0004
-#define RADEON_FALLBACK_RENDER_MODE 0x0008
-#define RADEON_FALLBACK_BLEND_EQ 0x0010
-#define RADEON_FALLBACK_BLEND_FUNC 0x0020
-#define RADEON_FALLBACK_DISABLE 0x0040
-#define RADEON_FALLBACK_BORDER_MODE 0x0080
-
-/* The blit width for texture uploads
- */
-#define BLIT_WIDTH_BYTES 1024
-/* Use the templated vertex format:
- */
-#define COLOR_IS_RGBA
-#define TAG(x) radeon##x
-#include "tnl_dd/t_dd_vertex.h"
-#undef TAG
-
-typedef void (*radeon_tri_func) (radeonContextPtr,
- radeonVertex *,
- radeonVertex *, radeonVertex *);
-
-typedef void (*radeon_line_func) (radeonContextPtr,
- radeonVertex *, radeonVertex *);
+#include "radeon_common.h"
-typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
-struct radeon_colorbuffer_state {
- GLuint clear;
- int roundEnable;
-};
-
-struct radeon_depthbuffer_state {
- GLuint clear;
- GLfloat scale;
-};
+struct r100_context;
+typedef struct r100_context r100ContextRec;
+typedef struct r100_context *r100ContextPtr;
-struct radeon_scissor_state {
- drm_clip_rect_t rect;
- GLboolean enabled;
+#include "radeon_lock.h"
- GLuint numClipRects; /* Cliprects active */
- GLuint numAllocedClipRects; /* Cliprects available */
- drm_clip_rect_t *pClipRects;
-};
-struct radeon_stencilbuffer_state {
- GLboolean hwBuffer;
- GLuint clear; /* rb3d_stencilrefmask value */
-};
-struct radeon_stipple_state {
- GLuint mask[32];
-};
+#define R100_TEX_ALL 0x7
/* used for both tcl_vtx and vc_frmt tex bits (they are identical) */
#define RADEON_ST_BIT(unit) \
#define RADEON_Q_BIT(unit) \
(unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit))
-typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
-
-/* Texture object in locally shared texture space.
- */
-struct radeon_tex_obj {
- driTextureObject base;
-
- GLuint bufAddr; /* Offset to start of locally
- shared texture block */
-
- GLuint dirty_state; /* Flags (1 per texunit) for
- whether or not this texobj
- has dirty hardware state
- (pp_*) that needs to be
- brought into the
- texunit. */
-
- drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
- /* Six, for the cube faces */
-
- GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
-
- GLuint pp_txfilter; /* hardware register values */
- GLuint pp_txformat;
- GLuint pp_txoffset; /* Image location in texmem.
- All cube faces follow. */
- GLuint pp_txsize; /* npot only */
- GLuint pp_txpitch; /* npot only */
- GLuint pp_border_color;
- GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */
-
- GLboolean border_fallback;
-
- GLuint tile_bits; /* hw texture tile bits used on this texture */
-};
-
struct radeon_texture_env_state {
radeonTexObjPtr texobj;
GLenum format;
struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS];
};
-struct radeon_state_atom {
- struct radeon_state_atom *next, *prev;
- const char *name; /* for debug */
- int cmd_size; /* size in bytes */
- GLuint is_tcl;
- int *cmd; /* one or more cmd's */
- int *lastcmd; /* one or more cmd's */
- GLboolean dirty; /* dirty-mark in emit_state_list */
- GLboolean(*check) (GLcontext *); /* is this state active? */
-};
-
/* Trying to keep these relatively short as the variables are becoming
* extravagently long. Drop the driver name prefix off the front of
* everything - I think we know which driver we're in by now, and keep the
#define SHN_SHININESS 1
#define SHN_STATE_SIZE 2
-struct radeon_hw_state {
- /* Head of the linked list of state atoms. */
- struct radeon_state_atom atomlist;
+#define R100_QUERYOBJ_CMD_0 0
+#define R100_QUERYOBJ_DATA_0 1
+#define R100_QUERYOBJ_CMDSIZE 2
+
+#define STP_CMD_0 0
+#define STP_DATA_0 1
+#define STP_CMD_1 2
+#define STP_STATE_SIZE 35
+struct r100_hw_state {
/* Hardware state, stored as cmdbuf commands:
* -- Need to doublebuffer for
* - eliding noop statechange loops? (except line stipple count)
struct radeon_state_atom fog;
struct radeon_state_atom glt;
struct radeon_state_atom txr[3]; /* for NPOT */
+ struct radeon_state_atom stp;
+};
- int max_state_size; /* Number of bytes necessary for a full state emit. */
- GLboolean is_dirty, all_dirty;
+struct radeon_stipple_state {
+ GLuint mask[32];
};
-struct radeon_state {
- /* Derived state for internal purposes:
- */
- struct radeon_colorbuffer_state color;
- struct radeon_depthbuffer_state depth;
- struct radeon_scissor_state scissor;
- struct radeon_stencilbuffer_state stencil;
+struct r100_state {
struct radeon_stipple_state stipple;
struct radeon_texture_state texture;
};
-/* Need refcounting on dma buffers:
- */
-struct radeon_dma_buffer {
- int refcount; /* the number of retained regions in buf */
- drmBufPtr buf;
-};
-
-#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \
- (rvb)->address - rmesa->dma.buf0_address + \
- (rvb)->start)
-
-/* A retained region, eg vertices for indexed vertices.
- */
-struct radeon_dma_region {
- struct radeon_dma_buffer *buf;
- char *address; /* == buf->address */
- int start, end, ptr; /* offsets from start of buf */
- int aos_start;
- int aos_stride;
- int aos_size;
-};
-
-struct radeon_dma {
- /* Active dma region. Allocations for vertices and retained
- * regions come from here. Also used for emitting random vertices,
- * these may be flushed by calling flush_current();
- */
- struct radeon_dma_region current;
-
- void (*flush) (radeonContextPtr);
-
- char *buf0_address; /* start of buf[0], for index calcs */
- GLuint nr_released_bufs; /* flush after so many buffers released */
-};
-
-struct radeon_dri_mirror {
- __DRIcontextPrivate *context; /* DRI context */
- __DRIscreenPrivate *screen; /* DRI screen */
-
- /**
- * DRI drawable bound to this context for drawing.
- */
- __DRIdrawablePrivate *drawable;
-
- /**
- * DRI drawable bound to this context for reading.
- */
- __DRIdrawablePrivate *readable;
-
- drm_context_t hwContext;
- drm_hw_lock_t *hwLock;
- int fd;
- int drmMinor;
-};
-
#define RADEON_CMD_BUF_SZ (8*1024)
-
-struct radeon_store {
- GLuint statenr;
- GLuint primnr;
- char cmd_buf[RADEON_CMD_BUF_SZ];
- int cmd_used;
- int elts_start;
-};
-
+#define R200_ELT_BUF_SZ (8*1024)
/* radeon_tcl.c
*/
-struct radeon_tcl_info {
+struct r100_tcl_info {
GLuint vertex_format;
GLuint hw_primitive;
*/
GLvector4f ObjClean;
- struct radeon_dma_region *aos_components[8];
- GLuint nr_aos_components;
-
GLuint *Elts;
- struct radeon_dma_region indexed_verts;
- struct radeon_dma_region obj;
- struct radeon_dma_region rgba;
- struct radeon_dma_region spec;
- struct radeon_dma_region fog;
- struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS];
- struct radeon_dma_region norm;
+ int elt_cmd_offset;
+ int elt_cmd_start;
+ int elt_used;
};
/* radeon_swtcl.c
*/
-struct radeon_swtcl_info {
- GLuint RenderIndex;
- GLuint vertex_size;
+struct r100_swtcl_info {
GLuint vertex_format;
- struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
- GLuint vertex_attr_count;
-
GLubyte *verts;
/* Fallback rasterization functions
radeon_line_func draw_line;
radeon_tri_func draw_tri;
- GLuint hw_primitive;
- GLenum render_primitive;
- GLuint numverts;
-
/**
* Offset of the 4UB color data within a hardware (swtcl) vertex.
*/
GLuint specoffset;
GLboolean needproj;
-
- struct radeon_dma_region indexed_verts;
};
-struct radeon_ioctl {
- GLuint vertex_offset;
- GLuint vertex_size;
-};
-#define RADEON_MAX_PRIMS 64
-
-struct radeon_prim {
- GLuint start;
- GLuint end;
- GLuint prim;
-};
/* A maximum total of 20 elements per vertex: 3 floats for position, 3
* floats for normal, 4 floats for color, 4 bytes for secondary color,
*/
#define RADEON_MAX_VERTEX_SIZE 20
-struct radeon_context {
- GLcontext *glCtx; /* Mesa context */
+struct r100_context {
+ struct radeon_context radeon;
/* Driver and hardware state management
*/
- struct radeon_hw_state hw;
- struct radeon_state state;
-
- /* Texture object bookkeeping
- */
- unsigned nr_heaps;
- driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
- driTextureObject swapped;
- int texture_depth;
- float initialMaxAnisotropy;
-
- /* Rasterization and vertex state:
- */
- GLuint TclFallback;
- GLuint Fallback;
- GLuint NewGLState;
- DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
+ struct r100_hw_state hw;
+ struct r100_state state;
/* Vertex buffers
*/
struct radeon_ioctl ioctl;
- struct radeon_dma dma;
struct radeon_store store;
- /* A full state emit as of the first state emit in the main store, in case
- * the context is lost.
- */
- struct radeon_store backup_store;
-
- /* Page flipping
- */
- GLuint doPageFlip;
-
- /* Busy waiting
- */
- GLuint do_usleeps;
- GLuint do_irqs;
- GLuint irqsEmitted;
- drm_radeon_irq_wait_t iw;
-
- /* Drawable, cliprect and scissor information
- */
- GLuint numClipRects; /* Cliprects for the draw buffer */
- drm_clip_rect_t *pClipRects;
- unsigned int lastStamp;
- GLboolean lost_context;
- GLboolean save_on_next_emit;
- radeonScreenPtr radeonScreen; /* Screen private DRI data */
- drm_radeon_sarea_t *sarea; /* Private SAREA data */
/* TCL stuff
*/
GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS];
GLuint last_ReallyEnabled;
- /* VBI
- */
- int64_t swap_ust;
- int64_t swap_missed_ust;
-
- GLuint swap_count;
- GLuint swap_missed_count;
-
/* radeon_tcl.c
*/
- struct radeon_tcl_info tcl;
+ struct r100_tcl_info tcl;
/* radeon_swtcl.c
*/
- struct radeon_swtcl_info swtcl;
-
- /* Mirrors of some DRI state
- */
- struct radeon_dri_mirror dri;
-
- /* Configuration cache
- */
- driOptionCache optionCache;
+ struct r100_swtcl_info swtcl;
GLboolean using_hyperz;
GLboolean texmicrotile;
GLuint c_textureSwaps;
GLuint c_textureBytes;
GLuint c_vertexBuffers;
+
};
-#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx))
-
-static INLINE GLuint radeonPackColor(GLuint cpp,
- GLubyte r, GLubyte g,
- GLubyte b, GLubyte a)
-{
- switch (cpp) {
- case 2:
- return PACK_COLOR_565(r, g, b);
- case 4:
- return PACK_COLOR_8888(a, r, g, b);
- default:
- return 0;
- }
-}
+
+#define R100_CONTEXT(ctx) ((r100ContextPtr)(ctx->DriverCtx))
+
#define RADEON_OLD_PACKETS 1
-extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
-extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
- __DRIcontextPrivate * driContextPriv,
- void *sharedContextPrivate);
-extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv);
-extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
- int x, int y, int w, int h);
-extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
- __DRIdrawablePrivate * driDrawPriv,
- __DRIdrawablePrivate * driReadPriv);
-extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
-
-/* ================================================================
- * Debugging:
- */
-#define DO_DEBUG 1
-
-#if DO_DEBUG
-extern int RADEON_DEBUG;
-#else
-#define RADEON_DEBUG 0
-#endif
-
-#define DEBUG_TEXTURE 0x0001
-#define DEBUG_STATE 0x0002
-#define DEBUG_IOCTL 0x0004
-#define DEBUG_PRIMS 0x0008
-#define DEBUG_VERTS 0x0010
-#define DEBUG_FALLBACKS 0x0020
-#define DEBUG_VFMT 0x0040
-#define DEBUG_CODEGEN 0x0080
-#define DEBUG_VERBOSE 0x0100
-#define DEBUG_DRI 0x0200
-#define DEBUG_DMA 0x0400
-#define DEBUG_SANITY 0x0800
-#define DEBUG_SYNC 0x1000
+extern GLboolean r100CreateContext( const __GLcontextModes *glVisual,
+ __DRIcontext *driContextPriv,
+ void *sharedContextPrivate);
+
#endif /* __RADEON_CONTEXT_H__ */
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