* Jérôme Glisse <glisse@freedesktop.org>
*/
#include <errno.h>
-#include "r300_reg.h"
-#include "r300_emit.h"
-#include "r300_cmdbuf.h"
-#include "radeon_cs.h"
-#include "radeon_cs_legacy.h"
-#include "radeon_bo_legacy.h"
-#include "radeon_context.h"
+
+#include "radeon_bocs_wrapper.h"
struct cs_manager_legacy {
struct radeon_cs_manager base;
/* hack for scratch stuff */
uint32_t pending_age;
uint32_t pending_count;
+
+
};
struct cs_reloc_legacy {
return cs;
}
-static int cs_write_dword(struct radeon_cs *cs, uint32_t dword)
-{
- if (cs->cdw >= cs->ndw) {
- uint32_t tmp, *ptr;
- tmp = (cs->cdw + 1 + 0x3FF) & (~0x3FF);
- ptr = (uint32_t*)realloc(cs->packets, 4 * tmp);
- if (ptr == NULL) {
- return -ENOMEM;
- }
- cs->packets = ptr;
- cs->ndw = tmp;
- }
- cs->packets[cs->cdw++] = dword;
- if (cs->section) {
- cs->section_cdw++;
- }
- return 0;
-}
-
static int cs_write_reloc(struct radeon_cs *cs,
struct radeon_bo *bo,
- uint32_t start_offset,
- uint32_t end_offset,
uint32_t read_domain,
uint32_t write_domain,
uint32_t flags)
if (write_domain == RADEON_GEM_DOMAIN_CPU) {
return -EINVAL;
}
- /* check reloc window */
- if (end_offset > bo->size) {
- return -EINVAL;
- }
- if (start_offset > end_offset) {
- return -EINVAL;
- }
/* check if bo is already referenced */
for(i = 0; i < cs->crelocs; i++) {
uint32_t *indices;
if (relocs[i].base.bo->handle == bo->handle) {
- /* update start and end offset */
- if (start_offset < relocs[i].base.start_offset) {
- relocs[i].base.start_offset = start_offset;
- }
- if (end_offset > relocs[i].base.end_offset) {
- relocs[i].base.end_offset = end_offset;
- }
/* Check domains must be in read or write. As we check already
* checked that in argument one of the read or write domain was
* set we only need to check that if previous reloc as the read
relocs[i].base.read_domain |= read_domain;
relocs[i].base.write_domain |= write_domain;
/* save indice */
- relocs[i].cindices += 1;
+ relocs[i].cindices++;
indices = (uint32_t*)realloc(relocs[i].indices,
relocs[i].cindices * 4);
if (indices == NULL) {
}
cs->relocs = relocs;
relocs[cs->crelocs].base.bo = bo;
- relocs[cs->crelocs].base.start_offset = start_offset;
- relocs[cs->crelocs].base.end_offset = end_offset;
relocs[cs->crelocs].base.read_domain = read_domain;
relocs[cs->crelocs].base.write_domain = write_domain;
relocs[cs->crelocs].base.flags = flags;
cs->section_file = file;
cs->section_func = func;
cs->section_line = line;
+
+
+ if (cs->cdw + ndw > cs->ndw) {
+ uint32_t tmp, *ptr;
+ int num = (ndw > 0x3FF) ? ndw : 0x3FF;
+
+ tmp = (cs->cdw + 1 + num) & (~num);
+ ptr = (uint32_t*)realloc(cs->packets, 4 * tmp);
+ if (ptr == NULL) {
+ return -ENOMEM;
+ }
+ cs->packets = ptr;
+ cs->ndw = tmp;
+ }
+
return 0;
}
}
cs->section = 0;
if (cs->section_ndw != cs->section_cdw) {
- fprintf(stderr, "CS section size missmatch start at (%s,%s,%d)\n",
- cs->section_file, cs->section_func, cs->section_line);
+ fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n",
+ cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw);
fprintf(stderr, "CS section end at (%s,%s,%d)\n",
file, func, line);
return -EPIPE;
struct cs_reloc_legacy *relocs;
int i, j, r;
- if (!IS_R300_CLASS(csm->ctx->radeonScreen)) {
- /* FIXME: r300 only right now */
- return -EINVAL;
- }
csm = (struct cs_manager_legacy*)cs->csm;
relocs = (struct cs_reloc_legacy *)cs->relocs;
+ restart:
for (i = 0; i < cs->crelocs; i++) {
for (j = 0; j < relocs[i].cindices; j++) {
uint32_t soffset, eoffset;
- soffset = relocs[i].base.start_offset;
- eoffset = relocs[i].base.end_offset;
r = radeon_bo_legacy_validate(relocs[i].base.bo,
&soffset, &eoffset);
+ if (r == -EAGAIN)
+ goto restart;
if (r) {
fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
relocs[i].base.bo, soffset, eoffset);
}
cs->packets[relocs[i].indices[j]] += soffset;
if (cs->packets[relocs[i].indices[j]] >= eoffset) {
- radeon_bo_debug(relocs[i].base.bo, 12);
+ /* radeon_bo_debug(relocs[i].base.bo, 12); */
fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
relocs[i].base.bo, soffset, eoffset);
fprintf(stderr, "above end: %p 0x%08X 0x%08X\n",
return 0;
}
+static void dump_cmdbuf(struct radeon_cs *cs)
+{
+ int i;
+ for (i = 0; i < cs->cdw; i++){
+ fprintf(stderr,"%x: %08x\n", i, cs->packets[i]);
+ }
+
+}
static int cs_emit(struct radeon_cs *cs)
{
struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
uint64_t ull;
int r;
- /* please flush pipe do all pending work */
- cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
- R300_SC_SCREENDOOR, 1));
- cs_write_dword(cs, 0x0);
- cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
- R300_SC_SCREENDOOR, 1));
- cs_write_dword(cs, 0x00FFFFFF);
- cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
- R300_SC_HYPERZ, 1));
- cs_write_dword(cs, 0x0);
- cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
- R300_US_CONFIG, 1));
- cs_write_dword(cs, 0x0);
- cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
- R300_ZB_CNTL, 1));
- cs_write_dword(cs, 0x0);
- cs_write_dword(cs, cmdwait(csm->ctx->radeonScreen, R300_WAIT_3D));
- cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
- R300_RB3D_DSTCACHE_CTLSTAT, 1));
- cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
- cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
- R300_ZB_ZCACHE_CTLSTAT, 1));
- cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
- cs_write_dword(cs, cmdwait(csm->ctx->radeonScreen,
- R300_WAIT_3D | R300_WAIT_3D_CLEAN));
+ csm->ctx->vtbl.emit_cs_header(cs, csm->ctx);
/* append buffer age */
- age.scratch.cmd_type = R300_CMD_SCRATCH;
- /* Scratch register 2 corresponds to what radeonGetAge polls */
- csm->pending_age = 0;
- csm->pending_count = 1;
- ull = (uint64_t) (intptr_t) &csm->pending_age;
- age.scratch.reg = 2;
- age.scratch.n_bufs = 1;
- age.scratch.flags = 0;
- radeon_cs_write_dword(cs, age.u);
- radeon_cs_write_dword(cs, ull & 0xffffffff);
- radeon_cs_write_dword(cs, ull >> 32);
- radeon_cs_write_dword(cs, 0);
+ if (IS_R300_CLASS(csm->ctx->radeonScreen)) {
+ age.scratch.cmd_type = R300_CMD_SCRATCH;
+ /* Scratch register 2 corresponds to what radeonGetAge polls */
+ csm->pending_age = 0;
+ csm->pending_count = 1;
+ ull = (uint64_t) (intptr_t) &csm->pending_age;
+ age.scratch.reg = 2;
+ age.scratch.n_bufs = 1;
+ age.scratch.flags = 0;
+ radeon_cs_write_dword(cs, age.u);
+ radeon_cs_write_qword(cs, ull);
+ radeon_cs_write_dword(cs, 0);
+ }
r = cs_process_relocs(cs);
if (r) {
cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects;
}
+ //dump_cmdbuf(cs);
+
r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd));
if (r) {
return r;
}
+ if (!IS_R300_CLASS(csm->ctx->radeonScreen)) {
+ drm_radeon_irq_emit_t emit_cmd;
+ emit_cmd.irq_seq = &csm->pending_age;
+ r = drmCommandWrite(cs->csm->fd, DRM_RADEON_IRQ_EMIT, &emit_cmd, sizeof(emit_cmd));
+ if (r) {
+ return r;
+ }
+ }
cs_set_age(cs);
+
+ cs->csm->read_used = 0;
+ cs->csm->vram_write_used = 0;
+ cs->csm->gart_write_used = 0;
return 0;
}
+static void inline cs_free_reloc(void *relocs_p, int crelocs)
+{
+ struct cs_reloc_legacy *relocs = relocs_p;
+ int i;
+ if (!relocs_p)
+ return;
+ for (i = 0; i < crelocs; i++)
+ free(relocs[i].indices);
+}
+
static int cs_destroy(struct radeon_cs *cs)
{
+ cs_free_reloc(cs->relocs, cs->crelocs);
free(cs->relocs);
free(cs->packets);
free(cs);
static int cs_erase(struct radeon_cs *cs)
{
+ cs_free_reloc(cs->relocs, cs->crelocs);
free(cs->relocs);
cs->relocs_total_size = 0;
cs->relocs = NULL;
static int cs_need_flush(struct radeon_cs *cs)
{
- /* FIXME: we should get the texture heap size */
- return (cs->relocs_total_size > (7*1024*1024));
+ /* this function used to flush when the BO usage got to
+ * a certain size, now the higher levels handle this better */
+ return 0;
+}
+
+static void cs_print(struct radeon_cs *cs, FILE *file)
+{
+}
+
+static int cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_check *bos, int num_bo)
+{
+ struct radeon_cs_manager *csm = cs->csm;
+ int this_op_read = 0, this_op_gart_write = 0, this_op_vram_write = 0;
+ uint32_t read_domains, write_domain;
+ int i;
+ struct radeon_bo *bo;
+
+ /* check the totals for this operation */
+
+ if (num_bo == 0)
+ return 0;
+
+ /* prepare */
+ for (i = 0; i < num_bo; i++) {
+ bo = bos[i].bo;
+
+ bos[i].new_accounted = 0;
+ read_domains = bos[i].read_domains;
+ write_domain = bos[i].write_domain;
+
+ /* pinned bos don't count */
+ if (radeon_legacy_bo_is_static(bo))
+ continue;
+
+ /* already accounted this bo */
+ if (write_domain && (write_domain == bo->space_accounted))
+ continue;
+
+ if (read_domains && ((read_domains << 16) == bo->space_accounted))
+ continue;
+
+ if (bo->space_accounted == 0) {
+ if (write_domain == RADEON_GEM_DOMAIN_VRAM)
+ this_op_vram_write += bo->size;
+ else if (write_domain == RADEON_GEM_DOMAIN_GTT)
+ this_op_gart_write += bo->size;
+ else
+ this_op_read += bo->size;
+ bos[i].new_accounted = (read_domains << 16) | write_domain;
+ } else {
+ uint16_t old_read, old_write;
+
+ old_read = bo->space_accounted >> 16;
+ old_write = bo->space_accounted & 0xffff;
+
+ if (write_domain && (old_read & write_domain)) {
+ bos[i].new_accounted = write_domain;
+ /* moving from read to a write domain */
+ if (write_domain == RADEON_GEM_DOMAIN_VRAM) {
+ this_op_read -= bo->size;
+ this_op_vram_write += bo->size;
+ } else if (write_domain == RADEON_GEM_DOMAIN_VRAM) {
+ this_op_read -= bo->size;
+ this_op_gart_write += bo->size;
+ }
+ } else if (read_domains & old_write) {
+ bos[i].new_accounted = bo->space_accounted & 0xffff;
+ } else {
+ /* rewrite the domains */
+ if (write_domain != old_write)
+ fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write);
+ if (read_domains != old_read)
+ fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read);
+ return RADEON_CS_SPACE_FLUSH;
+ }
+ }
+ }
+
+ if (this_op_read < 0)
+ this_op_read = 0;
+
+ /* check sizes - operation first */
+ if ((this_op_read + this_op_gart_write > csm->gart_limit) ||
+ (this_op_vram_write > csm->vram_limit)) {
+ return RADEON_CS_SPACE_OP_TO_BIG;
+ }
+
+ if (((csm->vram_write_used + this_op_vram_write) > csm->vram_limit) ||
+ ((csm->read_used + csm->gart_write_used + this_op_gart_write + this_op_read) > csm->gart_limit)) {
+ return RADEON_CS_SPACE_FLUSH;
+ }
+
+ csm->gart_write_used += this_op_gart_write;
+ csm->vram_write_used += this_op_vram_write;
+ csm->read_used += this_op_read;
+ /* commit */
+ for (i = 0; i < num_bo; i++) {
+ bo = bos[i].bo;
+ bo->space_accounted = bos[i].new_accounted;
+ }
+
+ return RADEON_CS_SPACE_OK;
}
static struct radeon_cs_funcs radeon_cs_legacy_funcs = {
cs_create,
- cs_write_dword,
cs_write_reloc,
cs_begin,
cs_end,
cs_emit,
cs_destroy,
cs_erase,
- cs_need_flush
+ cs_need_flush,
+ cs_print,
+ cs_check_space
};
-struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx)
+struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx)
{
struct cs_manager_legacy *csm;
return (struct radeon_cs_manager*)csm;
}
-void radeon_cs_manager_legacy_shutdown(struct radeon_cs_manager *csm)
+void radeon_cs_manager_legacy_dtor(struct radeon_cs_manager *csm)
{
free(csm);
}
+
projects / mesa.git / blobdiff