raedon/r200/r300: mega-FBO commits.

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_fbo.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index 0e3ac9c405721c8dddd7b99917c0cb564f4ca45b..f914c8c8d07f391af08126106cec86747dabcd56 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -54,7 +54,6 @@ radeon_new_framebuffer(GLcontext *ctx, GLuint name)
 static void
 radeon_delete_renderbuffer(struct gl_renderbuffer *rb)
 {
-  GET_CURRENT_CONTEXT(ctx);
   struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
 
   ASSERT(rrb);
@@ -62,8 +61,6 @@ radeon_delete_renderbuffer(struct gl_renderbuffer *rb)
   if (rrb && rrb->bo) {
     radeon_bo_unref(rrb->bo);
   }
-
-
   _mesa_free(rrb);
 }
 
@@ -179,16 +176,20 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
                                              width, height);
    }
    else {
-     /* TODO Alloc a BO */
      uint32_t size = width * height * cpp;
+     uint32_t pitch = ((cpp * width + 63) & ~63) / cpp;
+
+     fprintf(stderr,"Allocating %d x %d radeon RBO (pitch %d)\n", width,
+         height, pitch);
 
+     rrb->pitch = pitch * cpp;
+     rrb->cpp = cpp;
      rrb->bo = radeon_bo_open(radeon->radeonScreen->bom,
                              0,
                              size,
                              0,
                              RADEON_GEM_DOMAIN_VRAM,
                              0);
-     //     rrb->bo = radeon_bo_open();
      rb->Width = width;
      rb->Height = height;
        return GL_TRUE;
@@ -251,7 +252,7 @@ radeon_nop_alloc_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
    return GL_FALSE;
 }
 
-struct gl_renderbuffer *
+struct radeon_renderbuffer *
 radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
 {
     struct radeon_renderbuffer *rrb;
@@ -321,7 +322,7 @@ radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
     rrb->base.GetPointer = radeon_get_pointer;
 
     rrb->bo = NULL;
-    return &rrb->base;
+    return rrb;
 }
 
 static struct gl_renderbuffer *
@@ -373,24 +374,35 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb,
                     struct gl_texture_image *texImage)
 {
    if (texImage->TexFormat == &_mesa_texformat_argb8888) {
+      rrb->cpp = 4;
       rrb->base._ActualFormat = GL_RGBA8;
       rrb->base._BaseFormat = GL_RGBA;
       rrb->base.DataType = GL_UNSIGNED_BYTE;
       DBG("Render to RGBA8 texture OK\n");
    }
+   else if (texImage->TexFormat == &_mesa_texformat_argb4444) {
+      rrb->cpp = 2;
+      rrb->base._ActualFormat = GL_RGBA4;
+      rrb->base._BaseFormat = GL_RGBA;
+      rrb->base.DataType = GL_UNSIGNED_BYTE;
+      DBG("Render to RGBA4 texture OK\n");
+   }
    else if (texImage->TexFormat == &_mesa_texformat_rgb565) {
+      rrb->cpp = 2;
       rrb->base._ActualFormat = GL_RGB5;
       rrb->base._BaseFormat = GL_RGB;
       rrb->base.DataType = GL_UNSIGNED_SHORT;
       DBG("Render to RGB5 texture OK\n");
    }
    else if (texImage->TexFormat == &_mesa_texformat_z16) {
+      rrb->cpp = 2;
       rrb->base._ActualFormat = GL_DEPTH_COMPONENT16;
       rrb->base._BaseFormat = GL_DEPTH_COMPONENT;
       rrb->base.DataType = GL_UNSIGNED_SHORT;
       DBG("Render to DEPTH16 texture OK\n");
    }
    else if (texImage->TexFormat == &_mesa_texformat_s8_z24) {
+      rrb->cpp = 4;
       rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
       rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT;
       rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT;
@@ -402,6 +414,7 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb,
       return GL_FALSE;
    }
 
+   rrb->pitch = texImage->Width * rrb->cpp;
    rrb->base.InternalFormat = rrb->base._ActualFormat;
    rrb->base.Width = texImage->Width;
    rrb->base.Height = texImage->Height;
@@ -498,7 +511,6 @@ radeon_render_texture(GLcontext * ctx,
       radeon_bo_ref(rrb->bo);
    }
 
-#if 0
    /* compute offset of the particular 2D image within the texture region */
    imageOffset = radeon_miptree_image_offset(radeon_image->mt,
                                             att->CubeMapFace,
@@ -511,8 +523,8 @@ radeon_render_texture(GLcontext * ctx,
    }
 
    /* store that offset in the region */
-   radeon_image->mt->draw_offset = imageOffset;
-#endif
+   rrb->draw_offset = imageOffset;
+
    /* update drawing region, etc */
    radeon_draw_buffer(ctx, fb);
 }
@@ -550,4 +562,13 @@ void radeon_fbo_init(struct radeon_context *radeon)
 }
 
   
-  
+void radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb,
+                               struct radeon_bo *bo)
+{
+  struct radeon_bo *old;
+  old = rb->bo;
+  rb->bo = bo;
+  radeon_bo_ref(bo);
+  if (old)
+    radeon_bo_unref(old);
+}