static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
const char * caller );
+static void print_state_atom( struct radeon_state_atom *state )
+{
+ int i;
+
+ fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size);
+
+ if (RADEON_DEBUG & DEBUG_VERBOSE)
+ for (i = 0 ; i < state->cmd_size ; i++)
+ fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]);
+
+}
+
static void radeonSaveHwState( radeonContextPtr rmesa )
{
struct radeon_state_atom *atom;
char * dest = rmesa->backup_store.cmd_buf;
+ if (RADEON_DEBUG & DEBUG_STATE)
+ fprintf(stderr, "%s\n", __FUNCTION__);
+
rmesa->backup_store.cmd_used = 0;
foreach( atom, &rmesa->hw.atomlist ) {
memcpy( dest, atom->cmd, size);
dest += size;
rmesa->backup_store.cmd_used += size;
+ if (RADEON_DEBUG & DEBUG_STATE)
+ print_state_atom( atom );
}
}
assert( rmesa->backup_store.cmd_used <= RADEON_CMD_BUF_SZ );
+ if (RADEON_DEBUG & DEBUG_STATE)
+ fprintf(stderr, "Returning to radeonEmitState\n");
}
/* At this point we were in FlushCmdBufLocked but we had lost our context, so
*/
static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa )
{
- GLuint nr_released_bufs, saved_cmd_used;
+ GLuint nr_released_bufs;
struct radeon_store saved_store;
if (rmesa->backup_store.cmd_used == 0)
saved_store = rmesa->store;
rmesa->dma.nr_released_bufs = 0;
rmesa->store = rmesa->backup_store;
- saved_cmd_used = rmesa->backup_store.cmd_used;
radeonFlushCmdBufLocked( rmesa, __FUNCTION__ );
- rmesa->backup_store.cmd_used = saved_cmd_used;
rmesa->dma.nr_released_bufs = nr_released_bufs;
rmesa->store = saved_store;
}
* Kernel command buffer handling
*/
-static void print_state_atom( struct radeon_state_atom *state )
-{
- int i;
-
- fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size);
-
- if (RADEON_DEBUG & DEBUG_VERBOSE)
- for (i = 0 ; i < state->cmd_size ; i++)
- fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]);
-
-}
-
/* The state atoms will be emitted in the order they appear in the atom list,
* so this step is important.
*/
rmesa->save_on_next_emit = GL_FALSE;
}
- if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
- return;
+ /* this code used to return here but now it emits zbs */
/* To avoid going across the entire set of states multiple times, just check
* for enough space for the case of emitting all state, and inline the
radeonEnsureCmdBufSpace(rmesa, rmesa->hw.max_state_size);
dest = rmesa->store.cmd_buf + rmesa->store.cmd_used;
+ /* We always always emit zbs, this is due to a bug found by keithw in
+ the hardware and rediscovered after Erics changes by me.
+ if you ever touch this code make sure you emit zbs otherwise
+ you get tcl lockups on at least M7/7500 class of chips - airlied */
+ rmesa->hw.zbs.dirty=1;
+
if (RADEON_DEBUG & DEBUG_STATE) {
foreach(atom, &rmesa->hw.atomlist) {
if (atom->dirty || rmesa->hw.all_dirty) {
fprintf(stderr, "%s\n", __FUNCTION__);
assert( rmesa->dma.flush == radeonFlushElts );
- rmesa->dma.flush = 0;
+ rmesa->dma.flush = NULL;
/* Cope with odd number of elts:
*/
cmd[1] |= (dwords - 3) << 16;
cmd[3] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT;
#endif
+
+ if (RADEON_DEBUG & DEBUG_SYNC) {
+ fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
+ radeonFinish( rmesa->glCtx );
+ }
}
if (ret)
fprintf(stderr, "drmCommandWrite: %d\n", ret);
+ if (RADEON_DEBUG & DEBUG_SYNC) {
+ fprintf(stderr, "\nSyncing in %s\n\n", __FUNCTION__);
+ radeonWaitForIdleLocked( rmesa );
+ }
+
out:
rmesa->store.primnr = 0;
rmesa->store.statenr = 0;
rmesa->dma.nr_released_bufs++;
}
- region->buf = 0;
+ region->buf = NULL;
region->start = 0;
}
* SwapBuffers with client-side throttling
*/
-static uint32_t radeonGetLastFrame (radeonContextPtr rmesa)
+static u_int32_t radeonGetLastFrame (radeonContextPtr rmesa)
{
unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
int ret;
- uint32_t frame;
+ u_int32_t frame;
if (rmesa->dri.screen->drmMinor >= 4) {
drm_radeon_getparam_t gp;
rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
+ rmesa->radeonScreen->fbLocation;
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
+ if (rmesa->sarea->tiling_enabled) {
+ rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
+ }
}
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
drm_radeon_sarea_t *sarea = rmesa->sarea;
unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
- uint32_t clear;
+ u_int32_t clear;
GLuint flags = 0;
GLuint color_mask = 0;
GLint ret, i;
__FUNCTION__, all, cx, cy, cw, ch );
}
- RADEON_FIREVERTICES( rmesa );
+ {
+ LOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( rmesa );
+ if ( dPriv->numClipRects == 0 )
+ return;
+ }
+
+ radeonFlush( ctx );
- if ( mask & DD_FRONT_LEFT_BIT ) {
+ if ( mask & BUFFER_BIT_FRONT_LEFT ) {
flags |= RADEON_FRONT;
color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- mask &= ~DD_FRONT_LEFT_BIT;
+ mask &= ~BUFFER_BIT_FRONT_LEFT;
}
- if ( mask & DD_BACK_LEFT_BIT ) {
+ if ( mask & BUFFER_BIT_BACK_LEFT ) {
flags |= RADEON_BACK;
color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- mask &= ~DD_BACK_LEFT_BIT;
+ mask &= ~BUFFER_BIT_BACK_LEFT;
}
- if ( mask & DD_DEPTH_BIT ) {
- if ( ctx->Depth.Mask ) flags |= RADEON_DEPTH; /* FIXME: ??? */
- mask &= ~DD_DEPTH_BIT;
+ if ( mask & BUFFER_BIT_DEPTH ) {
+ flags |= RADEON_DEPTH;
+ mask &= ~BUFFER_BIT_DEPTH;
}
- if ( (mask & DD_STENCIL_BIT) && rmesa->state.stencil.hwBuffer ) {
+ if ( (mask & BUFFER_BIT_STENCIL) && rmesa->state.stencil.hwBuffer ) {
flags |= RADEON_STENCIL;
- mask &= ~DD_STENCIL_BIT;
+ mask &= ~BUFFER_BIT_STENCIL;
}
if ( mask ) {
if ( !flags )
return;
+ if (rmesa->using_hyperz) {
+ flags |= RADEON_USE_COMP_ZBUF;
+/* if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)
+ flags |= RADEON_USE_HIERZ; */
+ if (!(rmesa->state.stencil.hwBuffer) ||
+ ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
+ ((rmesa->state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
+ flags |= RADEON_CLEAR_FASTZ;
+ }
+ }
/* Flip top to bottom */
cx += dPriv->x;
projects / mesa.git / blobdiff