static void radeonWaitForIdle( radeonContextPtr rmesa );
-
-/* =============================================================
- * Kernel command buffer handling
- */
+static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
+ const char * caller );
static void print_state_atom( struct radeon_state_atom *state )
{
}
-static void radeon_emit_state_list( radeonContextPtr rmesa,
- struct radeon_state_atom *list )
+static void radeonSaveHwState( radeonContextPtr rmesa )
{
- struct radeon_state_atom *state, *tmp;
- char *dest;
- int i, size, texunits;
-
- /* It appears that some permutations of state atoms lock up the
- * chip. Therefore we make sure that state atoms are emitted in a
- * fixed order. First mark all dirty state atoms and then go
- * through all state atoms in a well defined order and emit only
- * the marked ones.
- * FIXME: This requires knowledge of which state atoms exist.
- * FIXME: Is the zbs hack below still needed?
- */
- size = 0;
- foreach_s( state, tmp, list ) {
- if (state->check( rmesa->glCtx )) {
- size += state->cmd_size;
- state->dirty = GL_TRUE;
- move_to_head( &(rmesa->hw.clean), state );
- if (RADEON_DEBUG & DEBUG_STATE)
- print_state_atom( state );
+ struct radeon_state_atom *atom;
+ char * dest = rmesa->backup_store.cmd_buf;
+
+ if (RADEON_DEBUG & DEBUG_STATE)
+ fprintf(stderr, "%s\n", __FUNCTION__);
+
+ rmesa->backup_store.cmd_used = 0;
+
+ foreach( atom, &rmesa->hw.atomlist ) {
+ if ( atom->check( rmesa->glCtx ) ) {
+ int size = atom->cmd_size * 4;
+ memcpy( dest, atom->cmd, size);
+ dest += size;
+ rmesa->backup_store.cmd_used += size;
+ if (RADEON_DEBUG & DEBUG_STATE)
+ print_state_atom( atom );
}
- else if (RADEON_DEBUG & DEBUG_STATE)
- fprintf(stderr, "skip state %s\n", state->name);
}
- /* short cut */
- if (!size)
- return;
-
- dest = radeonAllocCmdBuf( rmesa, size * 4, __FUNCTION__);
- texunits = rmesa->glCtx->Const.MaxTextureUnits;
-
-#define EMIT_ATOM(ATOM) \
-do { \
- if (rmesa->hw.ATOM.dirty) { \
- rmesa->hw.ATOM.dirty = GL_FALSE; \
- memcpy( dest, rmesa->hw.ATOM.cmd, rmesa->hw.ATOM.cmd_size * 4); \
- dest += rmesa->hw.ATOM.cmd_size * 4; \
- } \
-} while (0)
-
- EMIT_ATOM (ctx);
- EMIT_ATOM (set);
- EMIT_ATOM (lin);
- EMIT_ATOM (msk);
- EMIT_ATOM (vpt);
- EMIT_ATOM (tcl);
- EMIT_ATOM (msc);
- for (i = 0; i < texunits; ++i) {
- EMIT_ATOM (tex[i]);
- EMIT_ATOM (txr[i]);
+
+ assert( rmesa->backup_store.cmd_used <= RADEON_CMD_BUF_SZ );
+ if (RADEON_DEBUG & DEBUG_STATE)
+ fprintf(stderr, "Returning to radeonEmitState\n");
+}
+
+/* At this point we were in FlushCmdBufLocked but we had lost our context, so
+ * we need to unwire our current cmdbuf, hook the one with the saved state in
+ * it, flush it, and then put the current one back. This is so commands at the
+ * start of a cmdbuf can rely on the state being kept from the previous one.
+ */
+static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa )
+{
+ GLuint nr_released_bufs;
+ struct radeon_store saved_store;
+
+ if (rmesa->backup_store.cmd_used == 0)
+ return;
+
+ if (RADEON_DEBUG & DEBUG_STATE)
+ fprintf(stderr, "Emitting backup state on lost context\n");
+
+ rmesa->lost_context = GL_FALSE;
+
+ nr_released_bufs = rmesa->dma.nr_released_bufs;
+ saved_store = rmesa->store;
+ rmesa->dma.nr_released_bufs = 0;
+ rmesa->store = rmesa->backup_store;
+ radeonFlushCmdBufLocked( rmesa, __FUNCTION__ );
+ rmesa->dma.nr_released_bufs = nr_released_bufs;
+ rmesa->store = saved_store;
+}
+
+/* =============================================================
+ * Kernel command buffer handling
+ */
+
+/* The state atoms will be emitted in the order they appear in the atom list,
+ * so this step is important.
+ */
+void radeonSetUpAtomList( radeonContextPtr rmesa )
+{
+ int i, mtu = rmesa->glCtx->Const.MaxTextureUnits;
+
+ make_empty_list(&rmesa->hw.atomlist);
+ rmesa->hw.atomlist.name = "atom-list";
+
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ctx);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.set);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lin);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msk);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.vpt);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tcl);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msc);
+ for (i = 0; i < mtu; ++i) {
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tex[i]);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.txr[i]);
}
- EMIT_ATOM (zbs);
- EMIT_ATOM (mtl);
- for (i = 0; i < 3 + texunits; ++i)
- EMIT_ATOM (mat[i]);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.zbs);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mtl);
+ for (i = 0; i < 3 + mtu; ++i)
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mat[i]);
for (i = 0; i < 8; ++i)
- EMIT_ATOM (lit[i]);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lit[i]);
for (i = 0; i < 6; ++i)
- EMIT_ATOM (ucp[i]);
- EMIT_ATOM (eye);
- EMIT_ATOM (grd);
- EMIT_ATOM (fog);
- EMIT_ATOM (glt);
-
-#undef EMIT_ATOM
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ucp[i]);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.eye);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.grd);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.fog);
+ insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.glt);
}
-
void radeonEmitState( radeonContextPtr rmesa )
{
- struct radeon_state_atom *state, *tmp;
+ struct radeon_state_atom *atom;
+ char *dest;
if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
fprintf(stderr, "%s\n", __FUNCTION__);
- /* Somewhat overkill:
- */
- if (rmesa->lost_context) {
- if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS|DEBUG_IOCTL))
- fprintf(stderr, "%s - lost context\n", __FUNCTION__);
+ if (rmesa->save_on_next_emit) {
+ radeonSaveHwState(rmesa);
+ rmesa->save_on_next_emit = GL_FALSE;
+ }
- foreach_s( state, tmp, &(rmesa->hw.clean) )
- move_to_tail(&(rmesa->hw.dirty), state );
+ /* this code used to return here but now it emits zbs */
- rmesa->lost_context = 0;
- }
- else if (1) {
- /* This is a darstardly kludge to work around a lockup that I
- * haven't otherwise figured out.
- */
- move_to_tail(&(rmesa->hw.dirty), &(rmesa->hw.zbs) );
+ /* To avoid going across the entire set of states multiple times, just check
+ * for enough space for the case of emitting all state, and inline the
+ * radeonAllocCmdBuf code here without all the checks.
+ */
+ radeonEnsureCmdBufSpace(rmesa, rmesa->hw.max_state_size);
+ dest = rmesa->store.cmd_buf + rmesa->store.cmd_used;
+
+ /* We always always emit zbs, this is due to a bug found by keithw in
+ the hardware and rediscovered after Erics changes by me.
+ if you ever touch this code make sure you emit zbs otherwise
+ you get tcl lockups on at least M7/7500 class of chips - airlied */
+ rmesa->hw.zbs.dirty=1;
+
+ if (RADEON_DEBUG & DEBUG_STATE) {
+ foreach(atom, &rmesa->hw.atomlist) {
+ if (atom->dirty || rmesa->hw.all_dirty) {
+ if (atom->check(rmesa->glCtx))
+ print_state_atom(atom);
+ else
+ fprintf(stderr, "skip state %s\n", atom->name);
+ }
+ }
}
- if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
- foreach_s( state, tmp, &(rmesa->hw.dirty) ) {
- if (state->is_tcl) {
- move_to_head( &(rmesa->hw.clean), state );
- }
- }
+ foreach(atom, &rmesa->hw.atomlist) {
+ if (rmesa->hw.all_dirty)
+ atom->dirty = GL_TRUE;
+ if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) &&
+ atom->is_tcl)
+ atom->dirty = GL_FALSE;
+ if (atom->dirty) {
+ if (atom->check(rmesa->glCtx)) {
+ int size = atom->cmd_size * 4;
+ memcpy(dest, atom->cmd, size);
+ dest += size;
+ rmesa->store.cmd_used += size;
+ atom->dirty = GL_FALSE;
+ }
+ }
}
- radeon_emit_state_list( rmesa, &rmesa->hw.dirty );
+ assert(rmesa->store.cmd_used <= RADEON_CMD_BUF_SZ);
+
+ rmesa->hw.is_dirty = GL_FALSE;
+ rmesa->hw.all_dirty = GL_FALSE;
}
-
-
/* Fire a section of the retained (indexed_verts) buffer as a regular
* primtive.
*/
fprintf(stderr, "%s\n", __FUNCTION__);
assert( rmesa->dma.flush == radeonFlushElts );
- rmesa->dma.flush = 0;
+ rmesa->dma.flush = NULL;
/* Cope with odd number of elts:
*/
cmd[1] |= (dwords - 3) << 16;
cmd[3] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT;
#endif
+
+ if (RADEON_DEBUG & DEBUG_SYNC) {
+ fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
+ radeonFinish( rmesa->glCtx );
+ }
}
(component[0]->aos_start + offset * component[0]->aos_stride * 4);
#else
drm_radeon_cmd_header_t *cmd;
- int sz = AOS_BUFSZ;
+ int sz = AOS_BUFSZ(nr);
int i;
int *tmp;
int ret, i;
drm_radeon_cmd_buffer_t cmd;
+ if (rmesa->lost_context)
+ radeonBackUpAndEmitLostStateLocked(rmesa);
+
if (RADEON_DEBUG & DEBUG_IOCTL) {
fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
if (ret)
fprintf(stderr, "drmCommandWrite: %d\n", ret);
+ if (RADEON_DEBUG & DEBUG_SYNC) {
+ fprintf(stderr, "\nSyncing in %s\n\n", __FUNCTION__);
+ radeonWaitForIdleLocked( rmesa );
+ }
+
out:
rmesa->store.primnr = 0;
rmesa->store.statenr = 0;
rmesa->store.cmd_used = 0;
rmesa->dma.nr_released_bufs = 0;
- /* Set lost_context so that the first state emit on the new buffer is a full
- * one. This is because the context might get lost while preparing the next
- * buffer, and when we lock and find out, we don't have the information to
- * recreate the state. This function should always be called before the new
- * buffer is begun, so it's sufficient to just set lost_context here.
- *
- * The alternative to this would be to copy out the state on unlock
- * (approximately) and if we did lose the context, dispatch a cmdbuf to reset
- * the state to that old copy before continuing with the accumulated command
- * buffer.
- */
- rmesa->lost_context = 1;
+ rmesa->save_on_next_emit = 1;
return ret;
}
rmesa->dma.nr_released_bufs++;
}
- region->buf = 0;
+ region->buf = NULL;
region->start = 0;
}
* SwapBuffers with client-side throttling
*/
-static uint32_t radeonGetLastFrame (radeonContextPtr rmesa)
+static u_int32_t radeonGetLastFrame (radeonContextPtr rmesa)
{
unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
int ret;
- uint32_t frame;
+ u_int32_t frame;
if (rmesa->dri.screen->drmMinor >= 4) {
drm_radeon_getparam_t gp;
}
rmesa->swap_ust = ust;
+ rmesa->hw.all_dirty = GL_TRUE;
}
void radeonPageFlip( const __DRIdrawablePrivate *dPriv )
rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
+ rmesa->radeonScreen->fbLocation;
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
+ if (rmesa->sarea->tiling_enabled) {
+ rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
+ }
}
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
drm_radeon_sarea_t *sarea = rmesa->sarea;
unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
- uint32_t clear;
+ u_int32_t clear;
GLuint flags = 0;
GLuint color_mask = 0;
GLint ret, i;
__FUNCTION__, all, cx, cy, cw, ch );
}
- RADEON_FIREVERTICES( rmesa );
+ {
+ LOCK_HARDWARE( rmesa );
+ UNLOCK_HARDWARE( rmesa );
+ if ( dPriv->numClipRects == 0 )
+ return;
+ }
+
+ radeonFlush( ctx );
- if ( mask & DD_FRONT_LEFT_BIT ) {
+ if ( mask & BUFFER_BIT_FRONT_LEFT ) {
flags |= RADEON_FRONT;
color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- mask &= ~DD_FRONT_LEFT_BIT;
+ mask &= ~BUFFER_BIT_FRONT_LEFT;
}
- if ( mask & DD_BACK_LEFT_BIT ) {
+ if ( mask & BUFFER_BIT_BACK_LEFT ) {
flags |= RADEON_BACK;
color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- mask &= ~DD_BACK_LEFT_BIT;
+ mask &= ~BUFFER_BIT_BACK_LEFT;
}
- if ( mask & DD_DEPTH_BIT ) {
- if ( ctx->Depth.Mask ) flags |= RADEON_DEPTH; /* FIXME: ??? */
- mask &= ~DD_DEPTH_BIT;
+ if ( mask & BUFFER_BIT_DEPTH ) {
+ flags |= RADEON_DEPTH;
+ mask &= ~BUFFER_BIT_DEPTH;
}
- if ( (mask & DD_STENCIL_BIT) && rmesa->state.stencil.hwBuffer ) {
+ if ( (mask & BUFFER_BIT_STENCIL) && rmesa->state.stencil.hwBuffer ) {
flags |= RADEON_STENCIL;
- mask &= ~DD_STENCIL_BIT;
+ mask &= ~BUFFER_BIT_STENCIL;
}
if ( mask ) {
if ( !flags )
return;
+ if (rmesa->using_hyperz) {
+ flags |= RADEON_USE_COMP_ZBUF;
+/* if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)
+ flags |= RADEON_USE_HIERZ; */
+ if (!(rmesa->state.stencil.hwBuffer) ||
+ ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
+ ((rmesa->state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
+ flags |= RADEON_CLEAR_FASTZ;
+ }
+ }
/* Flip top to bottom */
cx += dPriv->x;
cy = dPriv->y + dPriv->h - cy - ch;
- /* We have to emit state along with the clear, since the kernel relies on
- * some of it. The EmitState that was above RADEON_FIREVERTICES was an
- * attempt to do that, except that another context may come in and cause us
- * to lose our context while we're unlocked.
- */
- radeonEmitState( rmesa );
-
LOCK_HARDWARE( rmesa );
/* Throttle the number of clear ioctls we do.
}
UNLOCK_HARDWARE( rmesa );
+ rmesa->hw.all_dirty = GL_TRUE;
}
if (rmesa->dma.flush)
rmesa->dma.flush( rmesa );
- if (!is_empty_list(&rmesa->hw.dirty))
- radeonEmitState( rmesa );
+ radeonEmitState( rmesa );
if (rmesa->store.cmd_used)
radeonFlushCmdBuf( rmesa, __FUNCTION__ );
projects / mesa.git / blobdiff