i965: Trivial formatting changes in brw_draw.c

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_ioctl.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index 3b853e3c83dfb376960e2c3c8879d19456980847..58fb9f1c6b97d401079f9fcff3676c150c6cff42 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -173,7 +173,7 @@ void radeonFlushElts( struct gl_context *ctx )
    int dwords = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw);
 
    if (RADEON_DEBUG & RADEON_IOCTL)
-      fprintf(stderr, "%s\n", __FUNCTION__);
+      fprintf(stderr, "%s\n", __func__);
 
    assert( rmesa->radeon.dma.flush == radeonFlushElts );
    rmesa->radeon.dma.flush = NULL;
@@ -205,7 +205,7 @@ void radeonFlushElts( struct gl_context *ctx )
    END_BATCH();
 
    if (RADEON_DEBUG & RADEON_SYNC) {
-      fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
+      fprintf(stderr, "%s: Syncing\n", __func__);
       radeonFinish( &rmesa->radeon.glCtx );
    }
 
@@ -221,7 +221,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
    BATCH_LOCALS(&rmesa->radeon);
 
    if (RADEON_DEBUG & RADEON_IOCTL)
-      fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
+      fprintf(stderr, "%s %d prim %x\n", __func__, min_nr, primitive);
 
    assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
 
@@ -262,7 +262,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
 
    if (RADEON_DEBUG & RADEON_RENDER)
       fprintf(stderr, "%s: header prim %x \n",
-             __FUNCTION__, primitive);
+             __func__, primitive);
 
    assert(!rmesa->radeon.dma.flush);
    rmesa->radeon.glCtx.Driver.NeedFlush |= FLUSH_STORED_VERTICES;
@@ -284,7 +284,7 @@ void radeonEmitVertexAOS( r100ContextPtr rmesa,
 
    if (RADEON_DEBUG & (RADEON_PRIMS|RADEON_IOCTL))
       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
-             __FUNCTION__, vertex_size, offset);
+             __func__, vertex_size, offset);
 
    BEGIN_BATCH(7);
    OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, 2);
@@ -315,7 +315,7 @@ void radeonEmitAOS( r100ContextPtr rmesa,
    int i;
 
    if (RADEON_DEBUG & RADEON_IOCTL)
-      fprintf(stderr, "%s\n", __FUNCTION__);
+      fprintf(stderr, "%s\n", __func__);
 
    BEGIN_BATCH(sz+2+(nr * 2));
    OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, sz - 1);
@@ -399,7 +399,7 @@ static void radeonClear( struct gl_context *ctx, GLbitfield mask )
 
    if ( swmask ) {
       if (RADEON_DEBUG & RADEON_FALLBACKS)
-        fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, swmask);
+        fprintf(stderr, "%s: swrast clear, mask: %x\n", __func__, swmask);
       _swrast_Clear( ctx, swmask );
    }