remove accidentally commited printf for tiling support

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_ioctl.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index aa982cfef965121031fa7d1ddf7daf2ee688b7e9..8e411bdaa8fac069b018b3e6b00d1c0f86efc280 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -179,8 +179,7 @@ void radeonEmitState( radeonContextPtr rmesa )
       rmesa->save_on_next_emit = GL_FALSE;
    }
 
-   if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
-      return;
+   /* this code used to return here but now it emits zbs */
 
    /* To avoid going across the entire set of states multiple times, just check
     * for enough space for the case of emitting all state, and inline the
@@ -189,6 +188,12 @@ void radeonEmitState( radeonContextPtr rmesa )
    radeonEnsureCmdBufSpace(rmesa, rmesa->hw.max_state_size);
    dest = rmesa->store.cmd_buf + rmesa->store.cmd_used;
 
+   /* We always always emit zbs, this is due to a bug found by keithw in
+      the hardware and rediscovered after Erics changes by me.
+      if you ever touch this code make sure you emit zbs otherwise
+      you get tcl lockups on at least M7/7500 class of chips - airlied */
+   rmesa->hw.zbs.dirty=1;
+
    if (RADEON_DEBUG & DEBUG_STATE) {
       foreach(atom, &rmesa->hw.atomlist) {
         if (atom->dirty || rmesa->hw.all_dirty) {
@@ -310,6 +315,11 @@ void radeonFlushElts( radeonContextPtr rmesa )
    cmd[1] |= (dwords - 3) << 16;
    cmd[3] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT;
 #endif
+
+   if (RADEON_DEBUG & DEBUG_SYNC) {
+      fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
+      radeonFinish( rmesa->glCtx );
+   }
 }
 
 
@@ -580,6 +590,11 @@ static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
    if (ret)
       fprintf(stderr, "drmCommandWrite: %d\n", ret);
 
+   if (RADEON_DEBUG & DEBUG_SYNC) {
+      fprintf(stderr, "\nSyncing in %s\n\n", __FUNCTION__);
+      radeonWaitForIdleLocked( rmesa );
+   }
+
  out:
    rmesa->store.primnr = 0;
    rmesa->store.statenr = 0;
@@ -772,11 +787,11 @@ void radeonAllocDmaRegionVerts( radeonContextPtr rmesa,
  * SwapBuffers with client-side throttling
  */
 
-static uint32_t radeonGetLastFrame (radeonContextPtr rmesa) 
+static u_int32_t radeonGetLastFrame (radeonContextPtr rmesa) 
 {
    unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
    int ret;
-   uint32_t frame;
+   u_int32_t frame;
 
    if (rmesa->dri.screen->drmMinor >= 4) {
       drm_radeon_getparam_t gp;
@@ -996,6 +1011,9 @@ void radeonPageFlip( const __DRIdrawablePrivate *dPriv )
    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
                                           + rmesa->radeonScreen->fbLocation;
    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH]  = rmesa->state.color.drawPitch;
+   if (rmesa->sarea->tiling_enabled) {
+      rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
+   }
 }
 
 
@@ -1011,7 +1029,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
    __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
    drm_radeon_sarea_t *sarea = rmesa->sarea;
    unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
-   uint32_t clear;
+   u_int32_t clear;
    GLuint flags = 0;
    GLuint color_mask = 0;
    GLint ret, i;
@@ -1043,7 +1061,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
    }
 
    if ( mask & DD_DEPTH_BIT ) {
-      if ( ctx->Depth.Mask ) flags |= RADEON_DEPTH; /* FIXME: ??? */
+      flags |= RADEON_DEPTH;
       mask &= ~DD_DEPTH_BIT;
    }
 
@@ -1061,6 +1079,16 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
    if ( !flags ) 
       return;
 
+   if (rmesa->using_hyperz) {
+      flags |= RADEON_USE_COMP_ZBUF;
+/*      if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) 
+         flags |= RADEON_USE_HIERZ; */
+      if (!(rmesa->state.stencil.hwBuffer) ||
+        ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
+           ((rmesa->state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
+         flags |= RADEON_CLEAR_FASTZ;
+      }
+   }
 
    /* Flip top to bottom */
    cx += dPriv->x;