radeon: fix scissors harder.
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_ioctl.c
index a5e4df794153de72a872865fb8fabc7932d67762..9ced62418bd5f96d5ccf5c929c89b22440de9f85 100644 (file)
@@ -113,7 +113,7 @@ void radeonSetUpAtomList( r100ContextPtr rmesa )
    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.glt);
 }
 
-void radeonEmitScissor(r100ContextPtr rmesa)
+static void radeonEmitScissor(r100ContextPtr rmesa)
 {
     BATCH_LOCALS(&rmesa->radeon);
     if (!rmesa->radeon.radeonScreen->kernel_mm) {
@@ -127,8 +127,8 @@ void radeonEmitScissor(r100ContextPtr rmesa)
         OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) |
                   rmesa->radeon.state.scissor.rect.x1);
         OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
-        OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2 - 1) << 16) |
-                  (rmesa->radeon.state.scissor.rect.x2 - 1));
+        OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2) << 16) |
+                  (rmesa->radeon.state.scissor.rect.x2));
         END_BATCH();
     } else {
         BEGIN_BATCH(2);
@@ -273,7 +273,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
    } else {
      OUT_BATCH(rmesa->ioctl.vertex_offset);
    }
-   OUT_BATCH(0xffff);
+   OUT_BATCH(rmesa->ioctl.vertex_max);
    OUT_BATCH(vertex_format);
    OUT_BATCH(primitive |
             RADEON_CP_VC_CNTL_PRIM_WALK_IND |
@@ -342,6 +342,7 @@ void radeonEmitAOS( r100ContextPtr rmesa,
    rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo;
    rmesa->ioctl.vertex_offset =
      (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4);
+   rmesa->ioctl.vertex_max = rmesa->radeon.tcl.aos[0].count;
 #else
    BATCH_LOCALS(&rmesa->radeon);
    uint32_t voffset;