#include <sched.h>
#include <errno.h>
+#include "main/attrib.h"
+#include "main/enable.h"
+#include "main/blend.h"
+#include "main/bufferobj.h"
+#include "main/buffers.h"
+#include "main/depth.h"
+#include "main/shaders.h"
+#include "main/texstate.h"
+#include "main/varray.h"
+#include "glapi/dispatch.h"
+#include "swrast/swrast.h"
+#include "main/stencil.h"
+#include "main/matrix.h"
+
#include "main/glheader.h"
#include "main/imports.h"
#include "main/simple_list.h"
#if RADEON_OLD_PACKETS
BEGIN_BATCH(8);
OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 3);
- OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
+ if (!rmesa->radeon.radeonScreen->kernel_mm) {
+ OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
+ } else {
+ OUT_BATCH(rmesa->ioctl.vertex_offset);
+ }
+
OUT_BATCH(vertex_nr);
OUT_BATCH(vertex_format);
OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_LIST |
RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
(vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT));
+
+ if (rmesa->radeon.radeonScreen->kernel_mm) {
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
+ rmesa->ioctl.bo,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
+ }
+
END_BATCH();
#else
nr = rmesa->tcl.elt_used;
- rmesa->radeon.cmdbuf.cs->cdw += dwords;
+#if RADEON_OLD_PACKETS
+ if (rmesa->radeon.radeonScreen->kernel_mm) {
+ dwords -= 2;
+ }
+#endif
#if RADEON_OLD_PACKETS
cmd[1] |= (dwords + 3) << 16;
cmd[3] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT;
#endif
+ rmesa->radeon.cmdbuf.cs->cdw += dwords;
rmesa->radeon.cmdbuf.cs->section_cdw += dwords;
+
+#if RADEON_OLD_PACKETS
+ if (rmesa->radeon.radeonScreen->kernel_mm) {
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
+ rmesa->ioctl.bo,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
+ }
+#endif
+
END_BATCH();
if (RADEON_DEBUG & DEBUG_SYNC) {
#if RADEON_OLD_PACKETS
BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(align_min_nr)/4);
OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 0);
- OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
+ if (!rmesa->radeon.radeonScreen->kernel_mm) {
+ OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
+ } else {
+ OUT_BATCH(rmesa->ioctl.vertex_offset);
+ }
OUT_BATCH(0xffff);
OUT_BATCH(vertex_format);
OUT_BATCH(primitive |
{
#if RADEON_OLD_PACKETS
assert( nr == 1 );
- rmesa->ioctl.bo = rmesa->tcl.aos[0].bo;
+ rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo;
rmesa->ioctl.vertex_offset =
- (rmesa->tcl.aos[0].offset + offset * rmesa->tcl.aos[0].stride * 4);
+ (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4);
#else
BATCH_LOCALS(&rmesa->radeon);
uint32_t voffset;
if (!rmesa->radeon.radeonScreen->kernel_mm) {
for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
- (rmesa->tcl.aos[i].stride << 8) |
- (rmesa->tcl.aos[i + 1].components << 16) |
- (rmesa->tcl.aos[i + 1].stride << 24));
+ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+ (rmesa->radeon.tcl.aos[i].stride << 8) |
+ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[i].bo,
+ rmesa->radeon.tcl.aos[i].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[i+1].bo,
+ rmesa->radeon.tcl.aos[i+1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
- OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
- (rmesa->tcl.aos[nr - 1].stride << 8));
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH_RELOC(voffset,
- rmesa->tcl.aos[nr - 1].bo,
+ rmesa->radeon.tcl.aos[nr - 1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
} else {
for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
- (rmesa->tcl.aos[i].stride << 8) |
- (rmesa->tcl.aos[i + 1].components << 16) |
- (rmesa->tcl.aos[i + 1].stride << 24));
+ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+ (rmesa->radeon.tcl.aos[i].stride << 8) |
+ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH(voffset);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH(voffset);
}
if (nr & 1) {
- OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
- (rmesa->tcl.aos[nr - 1].stride << 8));
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH(voffset);
}
for (i = 0; i + 1 < nr; i += 2) {
- voffset = rmesa->tcl.aos[i + 0].offset +
- offset * 4 * rmesa->tcl.aos[i + 0].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[i+0].bo,
+ rmesa->radeon.tcl.aos[i+0].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
- voffset = rmesa->tcl.aos[i + 1].offset +
- offset * 4 * rmesa->tcl.aos[i + 1].stride;
+ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[i+1].bo,
+ rmesa->radeon.tcl.aos[i+1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
- voffset = rmesa->tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
+ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->tcl.aos[nr-1].bo,
+ rmesa->radeon.tcl.aos[nr-1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
*/
#define RADEON_MAX_CLEARS 256
-static void radeonClear( GLcontext *ctx, GLbitfield mask )
+static void radeonUserClear(GLcontext *ctx, GLuint mask)
{
- r100ContextPtr rmesa = R100_CONTEXT(ctx);
+ radeon_clear_tris(ctx, mask);
+}
+
+static void radeonKernelClear(GLcontext *ctx, GLuint flags)
+{
+ r100ContextPtr rmesa = R100_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
uint32_t clear;
- GLuint flags = 0;
- GLuint color_mask = 0;
GLint ret, i;
GLint cx, cy, cw, ch;
- if ( RADEON_DEBUG & DEBUG_IOCTL ) {
- fprintf( stderr, "radeonClear\n");
- }
-
- {
- LOCK_HARDWARE( &rmesa->radeon );
- UNLOCK_HARDWARE( &rmesa->radeon );
- if ( dPriv->numClipRects == 0 )
- return;
- }
-
- radeonFlush( ctx );
-
- if ( mask & BUFFER_BIT_FRONT_LEFT ) {
- flags |= RADEON_FRONT;
- color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- mask &= ~BUFFER_BIT_FRONT_LEFT;
- }
-
- if ( mask & BUFFER_BIT_BACK_LEFT ) {
- flags |= RADEON_BACK;
- color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- mask &= ~BUFFER_BIT_BACK_LEFT;
- }
-
- if ( mask & BUFFER_BIT_DEPTH ) {
- flags |= RADEON_DEPTH;
- mask &= ~BUFFER_BIT_DEPTH;
- }
-
- if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) {
- flags |= RADEON_STENCIL;
- mask &= ~BUFFER_BIT_STENCIL;
- }
-
- if ( mask ) {
- if (RADEON_DEBUG & DEBUG_FALLBACKS)
- fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
- _swrast_Clear( ctx, mask );
- }
-
- if ( !flags )
- return;
-
- if (rmesa->using_hyperz) {
- flags |= RADEON_USE_COMP_ZBUF;
-/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL)
- flags |= RADEON_USE_HIERZ; */
- if (!(rmesa->radeon.state.stencil.hwBuffer) ||
- ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
- ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
- flags |= RADEON_CLEAR_FASTZ;
- }
- }
-
LOCK_HARDWARE( &rmesa->radeon );
/* compute region after locking: */
exit( 1 );
}
}
-
UNLOCK_HARDWARE( &rmesa->radeon );
- rmesa->radeon.hw.all_dirty = GL_TRUE;
+}
+
+static void radeonClear( GLcontext *ctx, GLbitfield mask )
+{
+ r100ContextPtr rmesa = R100_CONTEXT(ctx);
+ __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+ GLuint flags = 0;
+ GLuint color_mask = 0;
+ GLuint orig_mask = mask;
+
+ if ( RADEON_DEBUG & DEBUG_IOCTL ) {
+ fprintf( stderr, "radeonClear\n");
+ }
+
+ {
+ LOCK_HARDWARE( &rmesa->radeon );
+ UNLOCK_HARDWARE( &rmesa->radeon );
+ if ( dPriv->numClipRects == 0 )
+ return;
+ }
+
+ radeon_firevertices(&rmesa->radeon);
+
+ if ( mask & BUFFER_BIT_FRONT_LEFT ) {
+ flags |= RADEON_FRONT;
+ color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
+ mask &= ~BUFFER_BIT_FRONT_LEFT;
+ }
+
+ if ( mask & BUFFER_BIT_BACK_LEFT ) {
+ flags |= RADEON_BACK;
+ color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
+ mask &= ~BUFFER_BIT_BACK_LEFT;
+ }
+
+ if ( mask & BUFFER_BIT_DEPTH ) {
+ flags |= RADEON_DEPTH;
+ mask &= ~BUFFER_BIT_DEPTH;
+ }
+
+ if ( (mask & BUFFER_BIT_STENCIL) ) {
+ flags |= RADEON_STENCIL;
+ mask &= ~BUFFER_BIT_STENCIL;
+ }
+
+ if ( mask ) {
+ if (RADEON_DEBUG & DEBUG_FALLBACKS)
+ fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
+ _swrast_Clear( ctx, mask );
+ }
+
+ if ( !flags )
+ return;
+
+ if (rmesa->using_hyperz) {
+ flags |= RADEON_USE_COMP_ZBUF;
+/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL)
+ flags |= RADEON_USE_HIERZ; */
+ if (((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
+ ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
+ flags |= RADEON_CLEAR_FASTZ;
+ }
+ }
+
+ if (rmesa->radeon.radeonScreen->kernel_mm)
+ radeonUserClear(ctx, orig_mask);
+ else {
+ radeonKernelClear(ctx, flags);
+ rmesa->radeon.hw.all_dirty = GL_TRUE;
+ }
}
void radeonInitIoctlFuncs( GLcontext *ctx )
projects / mesa.git / blobdiff