* Gareth Hughes <gareth@valinux.com>
* Keith Whitwell <keith@tungstengraphics.com>
*/
+
#include <sched.h>
-#include <errno.h>
+#include <errno.h>
#include "glheader.h"
#include "imports.h"
#include "radeon_tcl.h"
#include "radeon_sanity.h"
+#define STANDALONE_MMIO
#include "radeon_macros.h" /* for INREG() */
#include "vblank.h"
{
struct radeon_state_atom *state, *tmp;
char *dest;
-
- /* From Felix Kuhling: similar to some other lockups, glaxium will
- * lock with what we believe to be a normal command stream, but
- * sprinkling some magic waits arounds allows it to run
- * uninterrupted. This has a slight effect on q3 framerates, but
- * it might now be possible to remove the zbs hack, below.
- *
- * Felix reports that this can be narrowed down to just
- * tcl,tex0,tex1 state, but that's pretty much every statechange,
- * so let's just put the wait in always (unless Felix wants to
- * narrow it down further...)
+ int i, size, texunits;
+
+ /* It appears that some permutations of state atoms lock up the
+ * chip. Therefore we make sure that state atoms are emitted in a
+ * fixed order. First mark all dirty state atoms and then go
+ * through all state atoms in a well defined order and emit only
+ * the marked ones.
+ * FIXME: This requires knowledge of which state atoms exist.
+ * FIXME: Is the zbs hack below still needed?
*/
- if (1) {
- drmRadeonCmdHeader *cmd;
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, sizeof(*cmd),
- __FUNCTION__ );
- cmd->wait.cmd_type = RADEON_CMD_WAIT;
- cmd->wait.flags = RADEON_WAIT_3D;
- }
-
+ size = 0;
foreach_s( state, tmp, list ) {
if (state->check( rmesa->glCtx )) {
- dest = radeonAllocCmdBuf( rmesa, state->cmd_size * 4, __FUNCTION__);
- memcpy( dest, state->cmd, state->cmd_size * 4);
+ size += state->cmd_size;
+ state->dirty = GL_TRUE;
move_to_head( &(rmesa->hw.clean), state );
if (RADEON_DEBUG & DEBUG_STATE)
print_state_atom( state );
else if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "skip state %s\n", state->name);
}
+ /* short cut */
+ if (!size)
+ return;
+
+ dest = radeonAllocCmdBuf( rmesa, size * 4, __FUNCTION__);
+ texunits = rmesa->glCtx->Const.MaxTextureUnits;
+
+#define EMIT_ATOM(ATOM) \
+do { \
+ if (rmesa->hw.ATOM.dirty) { \
+ rmesa->hw.ATOM.dirty = GL_FALSE; \
+ memcpy( dest, rmesa->hw.ATOM.cmd, rmesa->hw.ATOM.cmd_size * 4); \
+ dest += rmesa->hw.ATOM.cmd_size * 4; \
+ } \
+} while (0)
+
+ EMIT_ATOM (ctx);
+ EMIT_ATOM (set);
+ EMIT_ATOM (lin);
+ EMIT_ATOM (msk);
+ EMIT_ATOM (vpt);
+ EMIT_ATOM (tcl);
+ EMIT_ATOM (msc);
+ for (i = 0; i < texunits; ++i) {
+ EMIT_ATOM (tex[i]);
+ EMIT_ATOM (txr[i]);
+ }
+ EMIT_ATOM (zbs);
+ EMIT_ATOM (mtl);
+ for (i = 0; i < 3 + texunits; ++i)
+ EMIT_ATOM (mat[i]);
+ for (i = 0; i < 8; ++i)
+ EMIT_ATOM (lit[i]);
+ for (i = 0; i < 6; ++i)
+ EMIT_ATOM (ucp[i]);
+ EMIT_ATOM (eye);
+ EMIT_ATOM (grd);
+ EMIT_ATOM (fog);
+ EMIT_ATOM (glt);
+
+#undef EMIT_ATOM
}
GLuint primitive,
GLuint vertex_nr )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
- assert(rmesa->dri.drmMinor >= 3);
assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
radeonEmitState( rmesa );
rmesa->store.cmd_used/4);
#if RADEON_OLD_PACKETS
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 6 * sizeof(*cmd),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 6 * sizeof(*cmd),
__FUNCTION__ );
cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
cmd[1].i = RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM | (3 << 16);
__FUNCTION__,
cmd[1].i, cmd[2].i, cmd[4].i, cmd[5].i);
#else
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 4 * sizeof(*cmd),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 4 * sizeof(*cmd),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
GLuint primitive,
GLuint min_nr )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
GLushort *retval;
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s %d\n", __FUNCTION__, min_nr);
- assert(rmesa->dri.drmMinor >= 3);
assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
radeonEmitState( rmesa );
#if RADEON_OLD_PACKETS
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa,
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa,
24 + min_nr*2,
__FUNCTION__ );
cmd[0].i = 0;
retval = (GLushort *)(cmd+6);
#else
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa,
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa,
16 + min_nr*2,
__FUNCTION__ );
cmd[0].i = 0;
rmesa->ioctl.vertex_size = vertex_size;
rmesa->ioctl.vertex_offset = offset;
#else
- drmRadeonCmdHeader *cmd;
- assert(rmesa->dri.drmMinor >= 3);
+ drm_radeon_cmd_header_t *cmd;
if (RADEON_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n",
__FUNCTION__, vertex_size, offset);
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 5 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 5 * sizeof(int),
__FUNCTION__ );
cmd[0].i = 0;
rmesa->ioctl.vertex_offset =
(component[0]->aos_start + offset * component[0]->aos_stride * 4);
#else
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
int sz = 3 + (nr/2 * 3) + (nr & 1) * 2;
int i;
int *tmp;
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s\n", __FUNCTION__);
- assert(rmesa->dri.drmMinor >= 3);
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, sz * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sz * sizeof(int),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
GLint dstx, GLint dsty,
GLuint w, GLuint h )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
assert( w < (1<<16) );
assert( h < (1<<16) );
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 8 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 8 * sizeof(int),
__FUNCTION__ );
void radeonEmitWait( radeonContextPtr rmesa, GLuint flags )
{
if (rmesa->dri.drmMinor >= 6) {
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 1 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 1 * sizeof(int),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
const char * caller )
{
int ret, i;
- drmRadeonCmdBuffer cmd;
+ drm_radeon_cmd_buffer_t cmd;
if (RADEON_DEBUG & DEBUG_IOCTL) {
fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
if (rmesa->state.scissor.enabled) {
cmd.nbox = rmesa->state.scissor.numClipRects;
- cmd.boxes = (drmClipRect *)rmesa->state.scissor.pClipRects;
+ cmd.boxes = rmesa->state.scissor.pClipRects;
} else {
cmd.nbox = rmesa->numClipRects;
- cmd.boxes = (drmClipRect *)rmesa->pClipRects;
+ cmd.boxes = rmesa->pClipRects;
}
ret = drmCommandWrite( rmesa->dri.fd,
int ret;
- assert (rmesa->dri.drmMinor >= 3);
-
LOCK_HARDWARE( rmesa );
ret = radeonFlushCmdBufLocked( rmesa, caller );
UNLOCK_HARDWARE( rmesa );
if (ret) {
- fprintf(stderr, "drmRadeonCmdBuffer: %d (exiting)\n", ret);
+ fprintf(stderr, "drm_radeon_cmd_buffer_t: %d (exiting)\n", ret);
exit(ret);
}
}
rmesa->dma.flush( rmesa );
if (--region->buf->refcount == 0) {
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA))
fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__,
region->buf->buf->idx);
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, sizeof(*cmd),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sizeof(*cmd),
__FUNCTION__ );
cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD;
cmd->dma.buf_idx = region->buf->buf->idx;
rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */
rmesa->dma.current.start =
rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7;
-
- if ( rmesa->dri.drmMinor < 3 )
- radeonRefillCurrentDmaRegion( rmesa );
}
void radeonAllocDmaRegionVerts( radeonContextPtr rmesa,
* SwapBuffers with client-side throttling
*/
-static CARD32 radeonGetLastFrame (radeonContextPtr rmesa)
+static uint32_t radeonGetLastFrame (radeonContextPtr rmesa)
{
unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
int ret;
- CARD32 frame;
+ uint32_t frame;
if (rmesa->dri.screen->drmMinor >= 4) {
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
gp.param = RADEON_PARAM_LAST_FRAME;
- gp.value = &frame;
+ gp.value = (int *)&frame;
ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_GETPARAM,
&gp, sizeof(gp) );
}
else
ret = -EINVAL;
-#ifndef __alpha__
if ( ret == -EINVAL ) {
frame = INREG( RADEON_LAST_FRAME_REG );
ret = 0;
}
-#endif
if ( ret ) {
- fprintf( stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, ret );
+ fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret );
exit(1);
}
static void radeonEmitIrqLocked( radeonContextPtr rmesa )
{
- drmRadeonIrqEmit ie;
+ drm_radeon_irq_emit_t ie;
int ret;
ie.irq_seq = &rmesa->iw.irq_seq;
ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_IRQ_EMIT,
&ie, sizeof(ie) );
if ( ret ) {
- fprintf( stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__, ret );
+ fprintf( stderr, "%s: drm_radeon_irq_emit_t: %d\n", __FUNCTION__, ret );
exit(1);
}
}
static void radeonWaitForFrameCompletion( radeonContextPtr rmesa )
{
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
if (rmesa->do_irqs) {
if (radeonGetLastFrame(rmesa) < sarea->last_frame) {
radeonContextPtr rmesa;
GLint nbox, i, ret;
GLboolean missed_target;
- uint64_t ust;
+ int64_t ust;
assert(dPriv);
assert(dPriv->driContextPriv);
rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
if ( RADEON_DEBUG & DEBUG_IOCTL ) {
- fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, rmesa->glCtx );
+ fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx );
}
RADEON_FIREVERTICES( rmesa );
for ( i = 0 ; i < nbox ; ) {
GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox );
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
GLint n = 0;
for ( ; i < nr ; i++ ) {
*/
if (dPriv->numClipRects)
{
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
b[0] = box[0];
rmesa->sarea->nbox = 1;
}
}
RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset;
+ rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
+ + rmesa->radeonScreen->fbLocation;
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
}
{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
- CARD32 clear;
+ uint32_t clear;
GLuint flags = 0;
GLuint color_mask = 0;
GLint ret, i;
int ret;
if (rmesa->dri.screen->drmMinor >= 4) {
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
gp.param = RADEON_PARAM_LAST_CLEAR;
- gp.value = &clear;
+ gp.value = (int *)&clear;
ret = drmCommandWriteRead( rmesa->dri.fd,
DRM_RADEON_GETPARAM, &gp, sizeof(gp) );
} else
ret = -EINVAL;
-#ifndef __alpha__
if ( ret == -EINVAL ) {
clear = INREG( RADEON_LAST_CLEAR_REG );
ret = 0;
}
-#endif
if ( ret ) {
- fprintf( stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, ret );
+ fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret );
exit(1);
}
if ( RADEON_DEBUG & DEBUG_IOCTL ) {
for ( i = 0 ; i < dPriv->numClipRects ; ) {
GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects );
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
- drmRadeonClearType clear;
- drmRadeonClearRect depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
+ drm_radeon_clear_t clear;
+ drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
GLint n = 0;
if ( !all ) {
n--;
b = rmesa->sarea->boxes;
for ( ; n >= 0 ; n-- ) {
- depth_boxes[n].f[RADEON_CLEAR_X1] = (float)b[n].x1;
- depth_boxes[n].f[RADEON_CLEAR_Y1] = (float)b[n].y1;
- depth_boxes[n].f[RADEON_CLEAR_X2] = (float)b[n].x2;
- depth_boxes[n].f[RADEON_CLEAR_Y2] = (float)b[n].y2;
- depth_boxes[n].f[RADEON_CLEAR_DEPTH] =
+ depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1;
+ depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
+ depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2;
+ depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2;
+ depth_boxes[n].f[CLEAR_DEPTH] =
(float)rmesa->state.depth.clear;
}
ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR,
- &clear, sizeof(drmRadeonClearType));
+ &clear, sizeof(drm_radeon_clear_t));
if ( ret ) {
UNLOCK_HARDWARE( rmesa );
if (rmesa->dma.flush)
rmesa->dma.flush( rmesa );
- if (rmesa->dri.drmMinor >= 3) {
- if (!is_empty_list(&rmesa->hw.dirty))
- radeonEmitState( rmesa );
+ if (!is_empty_list(&rmesa->hw.dirty))
+ radeonEmitState( rmesa );
- if (rmesa->store.cmd_used)
- radeonFlushCmdBuf( rmesa, __FUNCTION__ );
- }
+ if (rmesa->store.cmd_used)
+ radeonFlushCmdBuf( rmesa, __FUNCTION__ );
}
/* Make sure all commands have been sent to the hardware and have
projects / mesa.git / blobdiff