-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
#include "mtypes.h"
#include "array_cache/acache.h"
+#include "math/m_translate.h"
#include "tnl/tnl.h"
#include "tnl/t_pipeline.h"
-#include "tnl/t_imm_debug.h"
-
+#include "math/m_translate.h"
#include "radeon_context.h"
#include "radeon_state.h"
#include "radeon_ioctl.h"
#define RADEON_TCL_MAX_SETUP 13
-union emit_union { float f; GLuint ui; radeon_color_t specular; };
+union emit_union { float f; GLuint ui; radeon_color_t rgba; };
static struct {
void (*emit)( GLcontext *, GLuint, GLuint, void * );
#define DO_TEX3 0
#define GET_TEXSOURCE(n) n
-#define GET_UBYTE_COLOR_STORE() &RADEON_CONTEXT(ctx)->UbyteColor
-#define GET_UBYTE_SPEC_COLOR_STORE() &RADEON_CONTEXT(ctx)->UbyteSecondaryColor
-
-#define IMPORT_FLOAT_COLORS radeon_import_float_colors
-#define IMPORT_FLOAT_SPEC_COLORS radeon_import_float_spec_colors
/***********************************************************************
* Generate vertex emit functions *
RADEON_CP_VC_FRMT_ST0| \
RADEON_CP_VC_FRMT_ST1| \
RADEON_CP_VC_FRMT_N0)
-#define TAG(x) x##_rgpa_spec_st_st_n
+#define TAG(x) x##_rgba_spec_st_st_n
#include "radeon_maos_vbtmp.h"
#define IDX 10
RADEON_CP_VC_FRMT_ST1| \
RADEON_CP_VC_FRMT_Q1| \
RADEON_CP_VC_FRMT_N0)
-#define TAG(x) x##_w_rgpa_spec_stq_stq_n
+#define TAG(x) x##_w_rgba_spec_stq_stq_n
#include "radeon_maos_vbtmp.h"
init_rgba_st_n();
init_rgba_spec_st_st();
init_st_st_n();
- init_rgpa_spec_st_st_n();
+ init_rgba_spec_st_st_n();
init_rgba_stq();
init_rgba_stq_stq();
- init_w_rgpa_spec_stq_stq_n();
+ init_w_rgba_spec_stq_stq_n();
}
setup_tab[i].vertex_size * 4,
4);
+ /* The vertex code expects Obj to be clean to element 3. To fix
+ * this, add more vertex code (for obj-2, obj-3) or preferably move
+ * to maos.
+ */
+ if (VB->ObjPtr->size < 3 ||
+ (VB->ObjPtr->size == 3 &&
+ (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0))) {
+
+ _math_trans_4f( rmesa->tcl.ObjClean.data,
+ VB->ObjPtr->data,
+ VB->ObjPtr->stride,
+ GL_FLOAT,
+ VB->ObjPtr->size,
+ 0,
+ VB->Count );
+
+ switch (VB->ObjPtr->size) {
+ case 1:
+ _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 1);
+ case 2:
+ _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 2);
+ case 3:
+ if (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0) {
+ _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 3);
+ }
+ case 4:
+ default:
+ break;
+ }
+
+ VB->ObjPtr = &rmesa->tcl.ObjClean;
+ }
+
+
+
setup_tab[i].emit( ctx, 0, VB->Count,
rmesa->tcl.indexed_verts.address +
rmesa->tcl.indexed_verts.start );
{
radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
+#if 0
if (RADEON_DEBUG & DEBUG_VERTS)
_tnl_print_vert_flags( __FUNCTION__, newinputs );
+#endif
if (newinputs)
radeonReleaseDmaRegion( rmesa, &rmesa->tcl.indexed_verts, __FUNCTION__ );