dri/radeon: remove duplicated includes

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_maos_verts.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
index bb90a7b1117259a891be36d71ed8b7a6f6ddf1d1..ad3bc2d23db647d21759b2ea43b8e9ee730018a8 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
+++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
@@ -40,7 +40,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "math/m_translate.h"
 #include "tnl/tnl.h"
 #include "tnl/t_pipeline.h"
-#include "math/m_translate.h"
 #include "radeon_context.h"
 #include "radeon_state.h"
 #include "radeon_ioctl.h"
@@ -326,7 +325,7 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
 
    if (1) {
       req |= RADEON_CP_VC_FRMT_Z;
-      if (VB->ObjPtr->size == 4) {
+      if (VB->AttribPtr[_TNL_ATTRIB_POS]->size == 4) {
         req |= RADEON_CP_VC_FRMT_W0;
       }
    }
@@ -348,15 +347,15 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
         req |= RADEON_ST_BIT(unit);
         /* assume we need the 3rd coord if texgen is active for r/q OR at least
            3 coords are submitted. This may not be 100% correct */
-        if (VB->TexCoordPtr[unit]->size >= 3) {
+        if (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) {
            req |= RADEON_Q_BIT(unit);
            vtx |= RADEON_Q_BIT(unit);
         }
         if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) )
            vtx |= RADEON_Q_BIT(unit);
-        else if ((VB->TexCoordPtr[unit]->size >= 3) &&
+        else if ((VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) &&
                  ((ctx->Texture.Unit[unit]._ReallyEnabled & (TEXTURE_CUBE_BIT)) == 0)) {
-           GLuint swaptexmatcol = (VB->TexCoordPtr[unit]->size - 3);
+           GLuint swaptexmatcol = (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size - 3);
            if (((rmesa->NeedTexMatrix >> unit) & 1) &&
                 (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1)))
               radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ;
@@ -374,15 +373,15 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
         break;
 
    if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
-       rmesa->tcl.aos[0].bo)
+       rmesa->radeon.tcl.aos[0].bo)
       return;
 
-   if (rmesa->tcl.aos[0].bo)
+   if (rmesa->radeon.tcl.aos[0].bo)
       radeonReleaseArrays( ctx, ~0 );
 
    radeonAllocDmaRegion( &rmesa->radeon,
-                        &rmesa->tcl.aos[0].bo,
-                        &rmesa->tcl.aos[0].offset,
+                        &rmesa->radeon.tcl.aos[0].bo,
+                        &rmesa->radeon.tcl.aos[0].offset,
                         VB->Count * setup_tab[i].vertex_size * 4, 
                         4);
 
@@ -390,19 +389,19 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
     * this, add more vertex code (for obj-2, obj-3) or preferably move
     * to maos.  
     */
-   if (VB->ObjPtr->size < 3 || 
-       (VB->ObjPtr->size == 3 && 
+   if (VB->AttribPtr[_TNL_ATTRIB_POS]->size < 3 ||
+       (VB->AttribPtr[_TNL_ATTRIB_POS]->size == 3 &&
        (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0))) {
 
       _math_trans_4f( rmesa->tcl.ObjClean.data,
-                     VB->ObjPtr->data,
-                     VB->ObjPtr->stride,
+                     VB->AttribPtr[_TNL_ATTRIB_POS]->data,
+                     VB->AttribPtr[_TNL_ATTRIB_POS]->stride,
                      GL_FLOAT,
-                     VB->ObjPtr->size,
+                     VB->AttribPtr[_TNL_ATTRIB_POS]->size,
                      0,
                      VB->Count );
 
-      switch (VB->ObjPtr->size) {
+      switch (VB->AttribPtr[_TNL_ATTRIB_POS]->size) {
       case 1:
            _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 1);
       case 2:
@@ -416,29 +415,18 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
         break;
       }
 
-      VB->ObjPtr = &rmesa->tcl.ObjClean;
+      VB->AttribPtr[_TNL_ATTRIB_POS] = &rmesa->tcl.ObjClean;
    }
 
 
-
+   radeon_bo_map(rmesa->radeon.tcl.aos[0].bo, 1);
    setup_tab[i].emit( ctx, 0, VB->Count, 
-                     rmesa->tcl.aos[0].bo->ptr + rmesa->tcl.aos[0].offset);
-
-   //   rmesa->tcl.aos[0].size = setup_tab[i].vertex_size;
-   rmesa->tcl.aos[0].stride = setup_tab[i].vertex_size;
+                     rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset);
+   radeon_bo_unmap(rmesa->radeon.tcl.aos[0].bo);
+   //   rmesa->radeon.tcl.aos[0].size = setup_tab[i].vertex_size;
+   rmesa->radeon.tcl.aos[0].stride = setup_tab[i].vertex_size;
    rmesa->tcl.vertex_format = setup_tab[i].vertex_format;
-   rmesa->tcl.nr_aos_components = 1;
+   rmesa->radeon.tcl.aos_count = 1;
 }
 
 
-
-void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
-{
-   r100ContextPtr rmesa = R100_CONTEXT( ctx );
-   int i;
-
-   for (i = 0; i < rmesa->tcl.nr_aos_components; i++) {
-     radeon_bo_unref(rmesa->tcl.aos[i].bo);
-     rmesa->tcl.aos[i].bo = NULL;
-   }
-}