-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
* Keith Whitwell <keith@tungstengraphics.com>
*/
-#include "glheader.h"
-#include "imports.h"
-#include "mtypes.h"
+#include "main/glheader.h"
+#include "main/imports.h"
+#include "main/mtypes.h"
-#include "array_cache/acache.h"
+#include "vbo/vbo.h"
+#include "math/m_translate.h"
#include "tnl/tnl.h"
#include "tnl/t_pipeline.h"
-
+#include "math/m_translate.h"
#include "radeon_context.h"
#include "radeon_state.h"
#include "radeon_ioctl.h"
#include "radeon_maos.h"
-#define RADEON_TCL_MAX_SETUP 13
+#define RADEON_TCL_MAX_SETUP 19
union emit_union { float f; GLuint ui; radeon_color_t rgba; };
#define DO_W (IND & RADEON_CP_VC_FRMT_W0)
#define DO_RGBA (IND & RADEON_CP_VC_FRMT_PKCOLOR)
-#define DO_SPEC (IND & RADEON_CP_VC_FRMT_PKSPEC)
-#define DO_FOG (IND & RADEON_CP_VC_FRMT_PKSPEC)
+#define DO_SPEC_OR_FOG (IND & RADEON_CP_VC_FRMT_PKSPEC)
+#define DO_SPEC ((IND & RADEON_CP_VC_FRMT_PKSPEC) && \
+ (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR))
+#define DO_FOG ((IND & RADEON_CP_VC_FRMT_PKSPEC) && ctx->Fog.Enabled && \
+ (ctx->Fog.FogCoordinateSource == GL_FOG_COORD))
#define DO_TEX0 (IND & RADEON_CP_VC_FRMT_ST0)
#define DO_TEX1 (IND & RADEON_CP_VC_FRMT_ST1)
+#define DO_TEX2 (IND & RADEON_CP_VC_FRMT_ST2)
#define DO_PTEX (IND & RADEON_CP_VC_FRMT_Q0)
#define DO_NORM (IND & RADEON_CP_VC_FRMT_N0)
-#define DO_TEX2 0
#define DO_TEX3 0
#define GET_TEXSOURCE(n) n
#define TAG(x) x##_w_rgba_spec_stq_stq_n
#include "radeon_maos_vbtmp.h"
+#define IDX 13
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_PKCOLOR| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_ST2)
+#define TAG(x) x##_rgba_st_st_st
+#include "radeon_maos_vbtmp.h"
+
+#define IDX 14
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_PKCOLOR| \
+ RADEON_CP_VC_FRMT_PKSPEC| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_ST2)
+#define TAG(x) x##_rgba_spec_st_st_st
+#include "radeon_maos_vbtmp.h"
+
+#define IDX 15
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_ST2| \
+ RADEON_CP_VC_FRMT_N0)
+#define TAG(x) x##_st_st_st_n
+#include "radeon_maos_vbtmp.h"
+
+#define IDX 16
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_PKCOLOR| \
+ RADEON_CP_VC_FRMT_PKSPEC| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_ST2| \
+ RADEON_CP_VC_FRMT_N0)
+#define TAG(x) x##_rgba_spec_st_st_st_n
+#include "radeon_maos_vbtmp.h"
+
+#define IDX 17
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_PKCOLOR| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_Q0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_Q1| \
+ RADEON_CP_VC_FRMT_ST2| \
+ RADEON_CP_VC_FRMT_Q2)
+#define TAG(x) x##_rgba_stq_stq_stq
+#include "radeon_maos_vbtmp.h"
+
+#define IDX 18
+#define IND (RADEON_CP_VC_FRMT_XY| \
+ RADEON_CP_VC_FRMT_Z| \
+ RADEON_CP_VC_FRMT_W0| \
+ RADEON_CP_VC_FRMT_PKCOLOR| \
+ RADEON_CP_VC_FRMT_PKSPEC| \
+ RADEON_CP_VC_FRMT_ST0| \
+ RADEON_CP_VC_FRMT_Q0| \
+ RADEON_CP_VC_FRMT_ST1| \
+ RADEON_CP_VC_FRMT_Q1| \
+ RADEON_CP_VC_FRMT_ST2| \
+ RADEON_CP_VC_FRMT_Q2| \
+ RADEON_CP_VC_FRMT_N0)
+#define TAG(x) x##_w_rgba_spec_stq_stq_stq_n
+#include "radeon_maos_vbtmp.h"
init_rgba_stq();
init_rgba_stq_stq();
init_w_rgba_spec_stq_stq_n();
+ init_rgba_st_st_st();
+ init_rgba_spec_st_st_st();
+ init_st_st_st_n();
+ init_rgba_spec_st_st_st_n();
+ init_rgba_stq_stq_stq();
+ init_w_rgba_spec_stq_stq_stq_n();
}
void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+ r100ContextPtr rmesa = R100_CONTEXT(ctx);
struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb;
GLuint req = 0;
+ GLuint unit;
GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &
- ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1));
+ ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1|RADEON_TCL_VTX_Q2));
int i;
static int firsttime = 1;
init_tcl_verts();
firsttime = 0;
}
-
+
if (1) {
req |= RADEON_CP_VC_FRMT_Z;
if (VB->ObjPtr->size == 4) {
if (inputs & VERT_BIT_NORMAL) {
req |= RADEON_CP_VC_FRMT_N0;
}
-
+
if (inputs & VERT_BIT_COLOR0) {
req |= RADEON_CP_VC_FRMT_PKCOLOR;
}
- if (inputs & VERT_BIT_COLOR1) {
+ if (inputs & (VERT_BIT_COLOR1|VERT_BIT_FOG)) {
req |= RADEON_CP_VC_FRMT_PKSPEC;
}
- if (inputs & VERT_BIT_TEX0) {
- req |= RADEON_CP_VC_FRMT_ST0;
-
- if (VB->TexCoordPtr[0]->size == 4) {
- req |= RADEON_CP_VC_FRMT_Q0;
- vtx |= RADEON_TCL_VTX_Q0;
- }
- }
-
- if (inputs & VERT_BIT_TEX1) {
- req |= RADEON_CP_VC_FRMT_ST1;
-
- if (VB->TexCoordPtr[1]->size == 4) {
- req |= RADEON_CP_VC_FRMT_Q1;
- vtx |= RADEON_TCL_VTX_Q1;
+ for (unit = 0; unit < ctx->Const.MaxTextureUnits; unit++) {
+ if (inputs & VERT_BIT_TEX(unit)) {
+ req |= RADEON_ST_BIT(unit);
+ /* assume we need the 3rd coord if texgen is active for r/q OR at least
+ 3 coords are submitted. This may not be 100% correct */
+ if (VB->TexCoordPtr[unit]->size >= 3) {
+ req |= RADEON_Q_BIT(unit);
+ vtx |= RADEON_Q_BIT(unit);
+ }
+ if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) )
+ vtx |= RADEON_Q_BIT(unit);
+ else if ((VB->TexCoordPtr[unit]->size >= 3) &&
+ ((ctx->Texture.Unit[unit]._ReallyEnabled & (TEXTURE_CUBE_BIT)) == 0)) {
+ GLuint swaptexmatcol = (VB->TexCoordPtr[unit]->size - 3);
+ if (((rmesa->NeedTexMatrix >> unit) & 1) &&
+ (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1)))
+ radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ;
+ }
}
}
break;
if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
- rmesa->tcl.indexed_verts.buf)
+ rmesa->tcl.aos[0].bo)
return;
- if (rmesa->tcl.indexed_verts.buf)
+ if (rmesa->tcl.aos[0].bo)
radeonReleaseArrays( ctx, ~0 );
- radeonAllocDmaRegionVerts( rmesa,
- &rmesa->tcl.indexed_verts,
- VB->Count,
- setup_tab[i].vertex_size * 4,
- 4);
+ radeonAllocDmaRegion( &rmesa->radeon,
+ &rmesa->tcl.aos[0].bo,
+ &rmesa->tcl.aos[0].offset,
+ VB->Count * setup_tab[i].vertex_size * 4,
+ 4);
/* The vertex code expects Obj to be clean to element 3. To fix
* this, add more vertex code (for obj-2, obj-3) or preferably move
setup_tab[i].emit( ctx, 0, VB->Count,
- rmesa->tcl.indexed_verts.address +
- rmesa->tcl.indexed_verts.start );
+ rmesa->tcl.aos[0].bo->ptr + rmesa->tcl.aos[0].offset);
+ // rmesa->tcl.aos[0].size = setup_tab[i].vertex_size;
+ rmesa->tcl.aos[0].stride = setup_tab[i].vertex_size;
rmesa->tcl.vertex_format = setup_tab[i].vertex_format;
- rmesa->tcl.indexed_verts.aos_start = GET_START( &rmesa->tcl.indexed_verts );
- rmesa->tcl.indexed_verts.aos_size = setup_tab[i].vertex_size;
- rmesa->tcl.indexed_verts.aos_stride = setup_tab[i].vertex_size;
-
- rmesa->tcl.aos_components[0] = &rmesa->tcl.indexed_verts;
rmesa->tcl.nr_aos_components = 1;
}
void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
-#if 0
- if (RADEON_DEBUG & DEBUG_VERTS)
- _tnl_print_vert_flags( __FUNCTION__, newinputs );
-#endif
+ r100ContextPtr rmesa = R100_CONTEXT( ctx );
+ int i;
- if (newinputs)
- radeonReleaseDmaRegion( rmesa, &rmesa->tcl.indexed_verts, __FUNCTION__ );
+ for (i = 0; i < rmesa->tcl.nr_aos_components; i++) {
+ if (rmesa->tcl.aos[i].bo) {
+ radeon_bo_unref(rmesa->tcl.aos[i].bo);
+ rmesa->tcl.aos[i].bo = NULL;
+ }
+ }
}
projects / mesa.git / blobdiff